Bubble NoC – A Low Energy Network-on-Chip with Small Footprint and High Performance

<div>The Bubble NoC is based on simplicity and provides outstanding performance. Flow control is implemented by <i>bubbles</i>, which are inserted between the flits. The logic resembles a traffic situation where a vehicle only moves if the next position is empty. When a flit moves, a bubble is created behind it, and when there is a blocking the bubbles are collapsed as the flits behind are packed together. Even when the Bubble NoC is saturated, it degrades gracefully, and the execution continues.</div><div> Deterministic prerouting is used, with the address stored as markers in a 2 out of 32 code. The routing algorithm shifts the address one step at each hop and turns or finishes when a marker starts the address.</div><div> The physical implementation is a mesh of <i>streets</i> containing duplex links of 38 wires carrying 32-bit payload. Signaling is based on current injection that charges the wires. A switch is placed in a four-way crossing, with a fifth local connection into a street. The switch contains input registers for each approaching street. Straight through traffic is simply passed on, and a diagonal gate is used for turning traffic.</div><div> All switches are bidirectional transmission gates, and the control is distributed as a sidewalk in a few µm of the periphery surrounding the intersection. In a 14 nm technology, the streets are 8 μm wide, the crossing is 17 μm in square, the hop frequency 6.67 GHz and the energy for a datapath 4.1 fJ/bit/hop (150 µm).</div>

Bubble NoC – A Low Energy Network-on-Chip with Small Footprint and High Performance

<div>The Bubble NoC is based on simplicity and provides outstanding performance. Flow control is implemented by <i>bubbles</i>, which are inserted between the flits. The logic resembles a traffic situation where a vehicle only moves if the next position is empty. When a flit moves, a bubble is created behind it, and when there is a blocking the bubbles are collapsed as the flits behind are packed together. Even when the Bubble NoC is saturated, it degrades gracefully, and the execution continues.</div><div> Deterministic prerouting is used, with the address stored as markers in a 2 out of 32 code. The routing algorithm shifts the address one step at each hop and turns or finishes when a marker starts the address.</div><div> The physical implementation is a mesh of <i>streets</i> containing duplex links of 38 wires carrying 32-bit payload. Signaling is based on current injection that charges the wires. A switch is placed in a four-way crossing, with a fifth local connection into a street. The switch contains input registers for each approaching street. Straight through traffic is simply passed on, and a diagonal gate is used for turning traffic.</div><div> All switches are bidirectional transmission gates, and the control is distributed as a sidewalk in a few µm of the periphery surrounding the intersection. In a 14 nm technology, the streets are 8 μm wide, the crossing is 17 μm in square, the hop frequency 6.67 GHz and the energy for a datapath 4.1 fJ/bit/hop (150 µm).</div>

A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers

This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 µm HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of d<i>V</i>_SSF/dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM¹ and FoM² of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers

This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 µm HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of d<i>V</i>_SSF/dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM¹ and FoM² of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

Design and Analysis of an Energy Efficient 4-bit Barrel Shifter Circuits in 45nm Technology

In the design of any ALU, shift registers are generally used to perform addition (for carry movement), multiplication and for any floating point arithmetic. The shift registers currently used are made up of flip-flops which require n clock pulses for n shifts which can increase the delay. So, the aim is to design a high speed shift register i.e., barrel shifter which needs a single clock pulse for n shifts. In this paper, three types of Barrel shifter circuits called left rotator, right rotator and bidirectional rotators are designed in Cadence Virtuoso tool for 180nm and 45nm technology using universal gates (conventional model) and transmission gates. Compared to conventional design, the circuits of barrel shifters with transmission gates in 45nm technology require less power and reduced transistor count.The designed barrel shifter circuits are showing improved performance than conventional models already presented in the literature.

The Design of Low-Power High-Speed Two-Level Three Input XOR gate

The Large Fan-In and high performance gates are essential to make portable electronic devices. In this paper an efficient realization of three input two level XOR(Exclusive-OR) is presented. The design of low power and high speed proposed XOR gate involves the combination of pass and transmission gates. The main objective to achieve this is based on the selection of input signals to propagate and maintain the good logic swing. Two methods were used to design proposed XOR, one (i.e. Pass_gate) is purely based on pass transistors with 8 MOSFET’s and second method(Modified_Pass_gate) uses transmission gates with 12 transistors. The Modified_Pass_gate offers 86.14% and 6.66% of power dissipation reduction compared to static and Pass_gate XOR respectively and 77.18% and 50.94% less propagation delay compared to static and Pass_gate XOR respectively, at the supply voltage of 0.7v with input signal frequency of 3GHz. The simulation is performed based on 32nm technology node(PTM-models) using Hspice Synopsis simulation tool.

Design of Advanced 64-bit Full Adder in 45-nm Technology

This paper presents the design of a 64-bit parallel adder with 45_nm technology using cadence virtuoso tool. The proposed method uses the designed 1-bti full adder and the performance is compared with the other cadence virtuoso technologies i.e. 180-nm and 90-nm. Performance parameters such as average power, delay, PDP and transistor count are calculated and compared with the 180-nm and 90-nm technologies. The proposed method based on 45-nm technology at 1V supply exhibits the average power consumption as low as 0.114µW and less delay of 3.503ps which is obtained from the absorption of extremely feeble CMOS inverters together with physically powerful transmission gates. The full adder is designed by using XNOR module and transmission gates. The XNOR module is used to produce the output SUM and the transmission gates are used to produce the output Carryout.