Design of In-Memory Parallel-Prefix Adders

Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width (O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in O(log(n)) latency in the memory array.

COMPARISON AND ANALYSIS OF PERFORMANCE PARAMETERS OF BASIC ADDERS WITH SPARSE ADDER

Adders play a vital role in the design of a digital system using VLSI (Very Large Scale Integration) technique. Adders are the basic building block of ALU (Arithmetic Logic Unit) which is an important component of a processor. In this paper we are comparing and analyzing the performance parameters of basic adders like Ripple Carry Adder, Carry Select Adder, Carry Look Ahead Adder, Parallel Prefix Adder along with sparse adder. The above mentioned adders are implemented using 90nm technology in Xilinx ISE 14.7 Suite.

Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}

Magnitude comparison, sign detection and overflow detection are essential operations of residue number system (RNS) that are used in digital signal processing (DSP) applications. Moreover, sign detection attracts significant attention in RNS as it can also be used in division and magnitude comparison operations. However, these operations are not easy to perform in RNS. So, there is a need arise to propose a computationally advanced RNS based sign detector. This paper presents an area and power-efficient sign detection circuit for modulo {2ⁿ- 1, 2ⁿ, 2ⁿ + 1} using mixed radix conversion technique. The proposed sign detector is constructed using a carry save adder (CSA), a modified parallel prefix adder and a carry-generation circuit. Based on the synthesized results using synopsys design compiler, the introduced design offers better results in terms of the area required and power consumption. Although, the speed will remain the same when compared to the recent sign detectors for the same moduli set.

High-performance Block Cipher Using Flexible Architecture

Light weight cryptography has been a prominent sector in exploring the cryptanalytics in contemporary world. In this paper, an elevated production capable structure and pliant implementations of hardware by SPECK, which is a lightly weighted block cipher is presented. This lightly weighted SPECK can be accustomed to diminish the retardation of critical path, a tree structure for the realization of Sklansky adder which is an efficient parallel prefix adder operation is used.