An Analytic Cache Performance Model

Author(s):  
J. J. Stiffler
2021 ◽  
Vol 10 (5) ◽  
pp. 2910-2920
Author(s):  
Ogechukwu Kingsley Ugwueze ◽  
Chijindu C. V. ◽  
Udeze C. C. ◽  
Ahaneku A. M. ◽  
Eneh N. J. ◽  
...  

This paper presents a cache performance model for embedded systems. The need for efficient cache design in embedded systems has led to the exploration of various methods of design for optimal cache configurations for embedded processor. Better users’ experiences are realized by improving performance parameters of embedded systems. This work presents a cache hit rate estimation model for embedded systems that can be used to explore optimal cache configurations using Bourneli’s binomial cumulative probability based on application of reuse distance profiles. The model presented was evaluated using three mibench benchmarks which are bitcount, basicmath and FFT for 4kb, 8kb, 16kb, 32kb and 64kb sizes of cache under 2-way, 4-ways, 8-ways and 16-ways set associative configurations, all using least recently-used (LRU) replacement policy. The results were compared with the results obtained using sim-cheetah from simplescalar simulators suite. The mean errors for bitcount, basicmath, and FFT benchmarks are 0.0263%, 2.4476%, and 1.9000% respectively. Therefore, the mean error for the three benchmarks is equal to 1.4579%. The margin of errors in the results was below 5% and within the acceptable limits showing that the model can be used to estimate hit rates of cache and to explore cache design options.


2011 ◽  
Vol 4 ◽  
pp. 2146-2155 ◽  
Author(s):  
Ràul de la Cruz ◽  
Mauricio Araya-Polo

2020 ◽  
Author(s):  
Mª de la Cruz Déniz‐Déniz ◽  
Mª Katiuska Cabrera-Suárez ◽  
Josefa D. Martín-Santana

2013 ◽  
Vol 26 (2) ◽  
pp. 144-149
Author(s):  
Wei Sun ◽  
Jianping Wang ◽  
Qiyue Li ◽  
Zituo Qian ◽  
Chongwei Zhang

1991 ◽  
Author(s):  
Michael J. Coombs ◽  
Roger T. Hartley ◽  
Heather D. Pfeiffer

Sign in / Sign up

Export Citation Format

Share Document