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Design of Low Power SAR ADC with Two Different DAC Structure and Two Different SAR Logic Designs and Their Comparisons
Advances in Intelligent Systems and Computing - Intelligent Systems Design and Applications
◽
10.1007/978-3-030-16657-1_81
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2019
◽
pp. 864-874
Author(s):
Aruna Kumari Chirapangi
◽
G. M. G. Madhuri
◽
Praveen Kitti Burri
◽
Naga Lakshmi Kalyani Movva
Keyword(s):
Low Power
◽
Sar Adc
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Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application
2020 International Conference on Electronics, Information, and Communication (ICEIC)
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Sung Jin Kim
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A 0.7-V 0.6- $\mu \text{W}$ 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction
IEEE Journal of Solid-State Circuits
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◽
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◽
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...
Keyword(s):
Low Power
◽
Noise Reduction
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Statistical Estimation
◽
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Considerations for Design of High Speed High Resolution Low Power SAR ADC for Direct RF Sampling Receivers
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Author(s):
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Keyword(s):
High Resolution
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Low Power
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High Speed
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Ultra‐low‐voltage low‐power dynamic comparator with forward body bias scheme for SAR ADC
Electronics Letters
◽
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◽
2018
◽
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◽
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◽
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Young‐Ha Hwang
◽
Deog‐Kyoon Jeong
Keyword(s):
Low Power
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Low Voltage
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Sar Adc
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Forward Body Bias
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A 6-Bit Low Power SAR ADC
Communications in Computer and Information Science - Communication, Networks and Computing
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Author(s):
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Keyword(s):
Low Power
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LOW-POWER DYNAMIC COMPARATOR WITH HIGH PRECISION FOR SAR ADC
Turkish Journal of Engineering
◽
10.31127/tuje.625475
◽
2020
◽
Author(s):
Ersin Alaybeyoğlu
Keyword(s):
Low Power
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High Precision
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Sar Adc
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Dynamic Comparator
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◽
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Low Power
◽
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Low-power 10-bit SAR ADC using class-AB type amplifier for IoT applications
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10.1109/isocc.2017.8368864
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Khuram Shehzad
◽
Hye-Young Kang
◽
Deeksha Verma
◽
Young Jun Park
◽
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Low Power
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Sar Adc
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Design of Low Power SAR ADC Using Clock Retiming
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
◽
10.1109/isvlsi.2018.00042
◽
2018
◽
Author(s):
S Jalaja
◽
A M Vijaya Prakash
Keyword(s):
Low Power
◽
Sar Adc
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