0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of Ion/Ioff ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.