Cache Memory Systems

2020 ◽  
pp. 217-242
Author(s):  
Petro Lutsyk ◽  
Jonas Oberhauser ◽  
Wolfgang J. Paul
Keyword(s):  
Memory Systems ◽  
Cache Memory

Accurate low-cost methods for performance evaluation of cache memory systems

1988 ◽  
Vol 37 (11) ◽  
pp. 1325-1336 ◽  
Author(s):  
S. Laha ◽  
J.H. Patel ◽  
R.K. Iyer
Keyword(s):  
Performance Evaluation ◽  
Low Cost ◽  
Memory Systems ◽  
Cache Memory

scholarly journals Some preliminary results of memory cache analysis with the use of non-extensive

2017 ◽  
Vol 16 (2) ◽  
pp. 43
Author(s):  
Dominik Strzałka
Keyword(s):  
Operating Systems ◽  
Computer Systems ◽  
Memory Systems ◽  
Cache Memory ◽  
Preliminary Results ◽  
Memory Cache ◽  
Statistical Behavior ◽  
And Performance ◽  
Inherent Part ◽  
Different Parts

<p>The problem of modeling different parts of computer systems requires accurate statistical tools. Cache memory systems is an inherent part of nowadays computer systems, where the memory hierarchical structure plays a key point role in behavior and performance of the whole system. In the case of Windows operating systems, cache memory is a place in memory subsystem where the I/O system puts recently used data from disk. In paper some preliminary results about statistical behavior of one selected system counter behavior are presented. Obtained results shown that the real phenomena, which have appeared during human-computer interaction, can be expressed in terms of non-extensive statistics that is related to Tsallis proposal of new entropy definition.</p>

scholarly journals Unfavorable Strides in Cache Memory Systems (RNR Technical Report RNR-92-015)

1995 ◽  
Vol 4 (2) ◽  
pp. 53-58 ◽  
Author(s):  
David H. Bailey
Keyword(s):  
Computer System ◽  
Simple Formula ◽  
High Performance ◽  
Memory Systems ◽  
Cache Memory ◽  
Scientific Application ◽  
Technical Report ◽  
Cache Efficiency

An important issue in obtaining high performance on a scientific application running on a cache-based computer system is the behavior of the cache when data are accessed at a constant stride. Others who have discussed this issue have noted an odd phenomenon in such situations: A few particular innocent-looking strides result in sharply reduced cache efficiency. In this article, this problem is analyzed, and a simple formula is presented that accurately gives the cache efficiency for various cache parameters and data strides.

A fast 7.5 ns access 1K-bit RAM for cache-memory systems

1978 ◽  
Vol 13 (5) ◽  
pp. 656-663 ◽  
Author(s):  
K. Kawarada ◽  
M. Suzuki ◽  
H. Mukai ◽  
K. Toyoda ◽  
Y. Kondo
Keyword(s):  
Memory Systems ◽  
Cache Memory

scholarly journals MESI Cache Coherence Simulator for Teaching Purposes

2009 ◽  
Vol 12 (1) ◽  
Author(s):  
Juan Gómez-Luna ◽  
Ezequiel Herruzo ◽  
José Ignacio Benavides
Keyword(s):  
Cache Coherence ◽  
Computer Systems ◽  
Memory Systems ◽  
Memory System ◽  
Experimental Results ◽  
Cache Memory ◽  
Memory Location ◽  
Memory Coherence ◽  
Computational Systems ◽  
Short Explanation

Nowadays, the computational systems (multi and uniprocessors) need to avoid the cachecoherence problem. There are some techniques to solve this problem. The MESI cachecoherence protocol is one of them. This paper presents a simulator of the MESI protocolwhich is used for teaching the cache memory coherence on the computer systems withhierarchical memory system and for explaining the process of the cache memory location inmultilevel cache memory systems. The paper shows a description of the course in which thesimulator is used, a short explanation about the MESI protocol and how the simulatorworks. Then, some experimental results in a real teaching environment are described.

Cache-memory interfaces in compressed memory systems

2001 ◽  
Vol 50 (11) ◽  
pp. 1106-1116 ◽  
Author(s):  
C.D. Benveniste ◽  
P.A. Franaszek ◽  
J.T. Robinson
Keyword(s):  
Memory Systems ◽  
Cache Memory

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

2021 ◽  
pp. 2250004
Author(s):  
Jagannath Samanta ◽  
Akash Kewat
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
High Speed ◽  
Memory Systems ◽  
Cache Memory ◽  
Error Correction Codes ◽  
Parity Check Matrix ◽  
Single Error ◽  
Check Matrix ◽  
Field Programmable

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

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