ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer

One widely used metric that measures data locality is reuse distance —the number of unique memory locations that are accessed between two consecutive accesses to a particular memory location. State-of-the-art techniques that measure reuse distance in parallel applications rely on simulators or binary instrumentation tools that incur large performance and memory overheads. Moreover, the existing sampling-based tools are limited to measuring reuse distances of a single thread and discard interactions among threads in multi-threaded programs. In this work, we propose ReuseTracker —a fast and accurate reuse distance analyzer that leverages existing hardware features in commodity CPUs. ReuseTracker is designed for multi-threaded programs and takes cache-coherence effects into account. By utilizing hardware features like performance monitoring units and debug registers, ReuseTracker can accurately profile reuse distance in parallel applications with much lower overheads than existing tools. It introduces only 2.9× runtime and 2.8× memory overheads. Our tool achieves 92% accuracy when verified against a newly developed configurable benchmark that can generate a variety of different reuse distance patterns. We demonstrate the tool’s functionality with two use-case scenarios using PARSEC, Rodinia, and Synchrobench benchmark suites where ReuseTracker guides code refactoring in these benchmarks by detecting spatial reuses in shared caches that are also false sharing and successfully predicts whether some benchmarks in these suites can benefit from adjacent cache line prefetch optimization.

Understanding Users’ Behavior towards Applications Privacy Policies

Recently, smartphone usage has increased tremendously, and smartphones are being used as a requirement of daily life, equally by all age groups. Smartphone operating systems such as Android and iOS have made it possible for anyone with development skills to create apps for smartphones. This has enabled smartphone users to download and install applications from stores such as Google Play, App Store, and several other third-party sites. During installation, these applications request resource access permissions from users. The resources include hardware and software like contact, memory, location, managing phone calls, device state, messages, camera, etc. As per Google’s permission policy, it is the responsibility of the user to allow or deny any permissions requested by an app. This leads to serious privacy violation issues when an app gets illegal permission granted by a user (e.g., an app might request for granted map permission and there is no need for map permission in the app, and someone can thereby access your location by this app). This study investigates the behavior of the user when it comes to safeguarding their privacy while installing apps from Google Play. In this research, first, seven different applications with irrelevant permission requests were developed and uploaded to two different Play Store accounts. The apps were live for more than 12 months and data were collected through Play Store analytics as well as the apps’ policy page. The preliminary data analysis shows that only 20% of users showed concern regarding their privacy and security either through interaction with the development team through email exchange or through commenting on the platform and other means accordingly.

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

Purpose This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle. Design/methodology/approach A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles. Findings With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations. Originality/value This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

Efficient Design of Control Logic Block in Dual Port Memory

A dual port memory in QCA are a study of data in different ports, but the data conflicts are very difficult to identify. Dual port memory is mainly focused on the data priority. It can be generated from the design of the control logic block. Priority bit are used, where both ports access the same memory location. Dual port memory functionality can be identified with a priority bit. When the port having the same memory location, only the port having the high priority is selected and other port are discarded. But when the read operation are requested to both the ports at same locations, having no conflicts and both the ports are requested to perform read operations. Data conflicts on the SRAM cell can be overcome by discarding the lower priority completely. Priorities are defined in terms of the area and delay. The idea behind this work is to minimize the area and delay in the dual port memory and proposed a multilayer Cross-Over design to provide an efficiency to the dual port memory and simulation result of design are shown in QCA Designer Tool-2.0.

Assisting Students’ Understanding of Memory Location Concept through Visualization

Learning programming for the first time is very difficult to many students. This difficulty negatively influences the students’ interest in learning programming thus poses a challenge to the lecturers to maintain students’ active involvement in learning. Students find it difficult to grasp the abstract concept of memory location, thus affects their understanding in writing programs. A memory location simulation program (MeLSim) is proposed to assist students with a realistic and visual experience of the abstract memory location concept. The objectives of this research are to develop a memory location simulation program and to determine students' understanding of the memory location concept after using the simulation. The students were given a pre-test and then required to use MeLSim for two weeks. They were then given a post-test. It was found that, there is significant difference on median total scores before and after using MeLSim. From the results, it can be concluded that students’ using MeLSim improved their test scores. This research provides evidence that visualization can assist students in achieving better understanding of the lessons taught which in turn positively influence their test results.

Reduced Area and Low Power Implementation of FFT/IFFT Processor

The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.

Visual software system for memory interleaving simulation

This paper describes the visual software system for memory interleaving simulation (VSMIS), implemented for the purpose of the course Computer Architecture and Organization 1, at the School of Electrical Engineering, University of Belgrade. The simulator enables students to expand their knowledge through practical work in the laboratory, as well as through independent work at home. VSMIS gives users the possibility to initialize parts of the system and to control simulation steps. The user has the ability to monitor simulation through graphical representation. It is possible to navigate through the entire hierarchy of the system using simple navigation. During the simulation the user can observe and set the values of the memory location. At any time, the user can reset the simulation of the system and observe it for different memory states; in addition, it is possible to save the current state of the simulation and continue with the execution of the simulation later.

Monitoring Biosensors and Obtaining Data Using GSM Module

<p>The main focus of the project is to prevent the loss of human life against the discomfort and death caused by the lack of attention towards the patients due to the improper monitoring systems provided in the hospital. The aim of the project is to monitor the bio sensors attached to the persons in their body either internally or externally. The biosensors which are about to be used in this project are EEG sensor (electro encephalogram sensor). An ECG sensor (electro cardiogram sensor) which is very essential for a critical patient, this project also emphasizes on the extended design of a special type of sensor called the oxygen insensitive microscale biosensor which helps in the monitoring of constant oxygen supply in blood thereby detecting blood cancer at the earliest stage. The data from all the sensors are sent to a central wireless node through wifi. From the main node the data is sent to the control station of the hospital through zigbee as the coverage area of certain hospitals is more than the coverage area of a Bluetooth. The control station segregates the data of different patients and stores in the memory location. If any of the patient data exceeds the standard data fed to the control station by the doctor then a message will be sent to the mobile of the attendee and the doctor using the GSM control system.<em></em></p><p><em>Keywords: Biosensors, Raspberry pi (controller), GSM, Zigbee</em></p><p><em> </em></p>