scholarly journals MESI Cache Coherence Simulator for Teaching Purposes

2009 ◽  
Vol 12 (1) ◽  
Author(s):  
Juan Gómez-Luna ◽  
Ezequiel Herruzo ◽  
José Ignacio Benavides
Keyword(s):  
Cache Coherence ◽  
Computer Systems ◽  
Memory Systems ◽  
Memory System ◽  
Experimental Results ◽  
Cache Memory ◽  
Memory Location ◽  
Memory Coherence ◽  
Computational Systems ◽  
Short Explanation

Nowadays, the computational systems (multi and uniprocessors) need to avoid the cachecoherence problem. There are some techniques to solve this problem. The MESI cachecoherence protocol is one of them. This paper presents a simulator of the MESI protocolwhich is used for teaching the cache memory coherence on the computer systems withhierarchical memory system and for explaining the process of the cache memory location inmultilevel cache memory systems. The paper shows a description of the course in which thesimulator is used, a short explanation about the MESI protocol and how the simulatorworks. Then, some experimental results in a real teaching environment are described.

scholarly journals Some preliminary results of memory cache analysis with the use of non-extensive

2017 ◽  
Vol 16 (2) ◽  
pp. 43
Author(s):  
Dominik Strzałka
Keyword(s):  
Operating Systems ◽  
Computer Systems ◽  
Memory Systems ◽  
Cache Memory ◽  
Preliminary Results ◽  
Memory Cache ◽  
Statistical Behavior ◽  
And Performance ◽  
Inherent Part ◽  
Different Parts

<p>The problem of modeling different parts of computer systems requires accurate statistical tools. Cache memory systems is an inherent part of nowadays computer systems, where the memory hierarchical structure plays a key point role in behavior and performance of the whole system. In the case of Windows operating systems, cache memory is a place in memory subsystem where the I/O system puts recently used data from disk. In paper some preliminary results about statistical behavior of one selected system counter behavior are presented. Obtained results shown that the real phenomena, which have appeared during human-computer interaction, can be expressed in terms of non-extensive statistics that is related to Tsallis proposal of new entropy definition.</p>

scholarly journals Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1399
Author(s):  
Taepyeong Kim ◽  
Sangun Park ◽  
Yongbeom Cho
Keyword(s):  
High Speed ◽  
Memory Systems ◽  
Memory System ◽  
External Memory ◽  
Essential Factor ◽  
Wide Bandwidth ◽  
Reading And Writing ◽  
Data Skew ◽  
Lower Performance ◽  
Efficient Memory

In this study, a simple and effective memory system required for the implementation of an AI chip is proposed. To implement an AI chip, the use of internal or external memory is an essential factor, because the reading and writing of data in memory occurs a lot. Those memory systems that are currently used are large in design size and complex to implement in order to handle a high speed and a wide bandwidth. Therefore, depending on the AI application, there are cases where the circuit size of the memory system is larger than that of the AI core. In this study, SDRAM, which has a lower performance than the currently used memory system but does not have a problem in operating AI, was used and all circuits were implemented digitally for simple and efficient implementation. In particular, a delay controller was designed to reduce the error due to data skew inside the memory bus to ensure stability in reading and writing data. First of all, it verified the memory system based on the You Only Look Once (YOLO) algorithm in FPGA to confirm that the memory system proposed in AI works efficiently. Based on the proven memory system, we implemented a chip using Samsung Electronics’ 65 nm process and tested it. As a result, we designed a simple and efficient memory system for AI chip implementation and verified it with hardware.

scholarly journals Cooperative cache memory (CCM) based on the performance efficiency for 3D stacked memory system

2016 ◽  
Vol 13 (12) ◽  
pp. 20160276-20160276
Author(s):  
Hongyeol Lim ◽  
Gi-Ho Park
Keyword(s):  
Memory System ◽  
Cache Memory ◽  
Cooperative Cache ◽  
Stacked Memory

Within- and Between-Team Coordination via Transactive Memory Systems and Boundary Spanning

2018 ◽  
Vol 43 (5) ◽  
pp. 691-717 ◽  
Author(s):  
Joy Olabisi ◽  
Kyle Lewis
Keyword(s):  
Management Practices ◽  
Knowledge Exchange ◽  
Memory Systems ◽  
Boundary Spanning ◽  
Transactive Memory ◽  
Memory System ◽  
Transactive Memory Systems ◽  
Team Coordination ◽  
Transactive Memory System ◽  
Over Time

In this article, we suggest that the transactive memory system (TMS) and boundary-spanning literatures are useful for understanding how individuals in team-based collectives can be structured to improve within- and between-team coordination. We argue that such coordination can be facilitated—or thwarted—by boundary-spanning behaviors and patterns of knowledge exchange within and between teams. Our theorizing explains how an existing team TMS can offset the within-team coordination burdens typically associated with boundary spanning and we offer predictions about how these factors interrelate to affect TMS and coordination over time. Finally, our theory underscores significant implications and provides insights for how management practices might improve coordination within and between teams.

scholarly journals Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2158
Author(s):  
Jeong-Geun Kim ◽  
Shin-Dug Kim ◽  
Su-Kyung Yoon
Keyword(s):  
Performance Status ◽  
Random Access ◽  
Memory Systems ◽  
Memory System ◽  
Main Memory ◽  
Learning Method ◽  
Q Learning ◽  
Data Intensive ◽  
Big Data Applications ◽  
Non Volatile Memory

This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.

Adaptive memory systems for remembering the salient and the seemingly mundane

2016 ◽  
Vol 39 ◽  
Author(s):  
Maureen Ritchey ◽  
Vishnu P. Murty ◽  
Joseph E. Dunsmoor
Keyword(s):  
Memory Systems ◽  
Memory System ◽  
Adaptive Memory

AbstractIn an adaptive memory system, events should be prioritized in memory based on their own significance, as well as the significance of preceding or following events. Here we argue that tag-and-capture models complement the GANE (glutamate amplifies noradrenergic effects) model by describing a mechanism that supports the transfer of memory benefits from one event to the next.

Application-adaptive intelligent cache memory system

2002 ◽  
Vol 1 (1) ◽  
pp. 56-78 ◽  
Author(s):  
Jung-Hoon Lee ◽  
Shin-Dug Kim ◽  
Charles Weems
Keyword(s):  
Memory System ◽  
Cache Memory ◽  
Intelligent Cache

Accurate low-cost methods for performance evaluation of cache memory systems

1988 ◽  
Vol 37 (11) ◽  
pp. 1325-1336 ◽  
Author(s):  
S. Laha ◽  
J.H. Patel ◽  
R.K. Iyer
Keyword(s):  
Performance Evaluation ◽  
Low Cost ◽  
Memory Systems ◽  
Cache Memory
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