scholarly journals Test

2021 ◽  
pp. 381-391
Author(s):  
Peter Marwedel
Keyword(s):  
Physical System ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Fault Simulation ◽  
Fault Coverage ◽  
Fault Model ◽  
Pattern Generation ◽  
Signature Analysis ◽  
Fault Tolerant Systems ◽  
Random Patterns

AbstractUnfortunately, we cannot rely on designed and possibly already manufactured systems to operate as expected. These systems may have become defective during their use, or their function may have been compromised during the fabrication or their design. The purpose of testing is to verify whether or not an existing embedded/cyber-physical system can be operated as expected. In this chapter, we will present fundamental terms and techniques for testing. There will be a brief introduction to the aims of test pattern generation and their application. We will be introducing terms such as fault model, fault coverage, fault simulation, and fault injection. Also, we will be presenting techniques which improve testability, including the generation of pseudo-random patterns, and signature analysis. It would be beneficial to consider testability issues already during design. In case of fault-tolerant systems, resilience must be verified.

A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Extend ATPG Diagnostic Resolution in Localizing Faults

2019 ◽  
Author(s):  
Rommel Estores ◽  
Karo Vander Gucht
Keyword(s):  
Fault Injection ◽  
Fault Simulation ◽  
Fault Localization ◽  
Pattern Generation ◽  
Test Coverage ◽  
Actual Case ◽  
Electrical Failure ◽  
Starting Point ◽  
Diagnostic Resolution ◽  
Diagnosis Approach

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.

scholarly journals TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform

2021 ◽  
Vol 11 (3) ◽  
pp. 2704
Author(s):  
Sharath Kumar Y. N. ◽  
Dinesha P.
Keyword(s):  
Integrated Circuits ◽  
Digital Circuits ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Asynchronous Circuits ◽  
Fault Coverage ◽  
Asynchronous Circuit ◽  
Hardware Complexity ◽  
Transient Fault ◽  
Fault Tolerant System

Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.

INCORPORATING FAULT-TOLERANT FEATURES IN VLIW PROCESSORS

2005 ◽  
Vol 12 (05) ◽  
pp. 397-411
Author(s):  
YUNG-YUAN CHEN
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Fault Simulation ◽  
Error Recovery ◽  
Instruction Level Parallelism ◽  
Vliw Processors ◽  
Test Instruction ◽  
Vliw Processor ◽  
Level Parallelism

In recent years, very long instruction word (VLIW) processor has attracted much attention in that it offers a high instruction level parallelism and reduces the hardware design complexity. In this paper, we present two fault-tolerant schemes for VLIW processors. The first one is termed as test-instruction scheme which is based on the concept of instruction duplication to detect the errors. The process of test-instruction scheme consists of the error detection, error rollback recovery and reconfiguration. The second approach is called self-checking scheme which adopts the concept of self-checking logic to detect the errors. A real-time error recovery procedure is developed to conquer the errors. We implement the proposed designs of fault-tolerant VLIW processor in VHDL and employ the fault injection and fault simulation to validate our schemes. The main contribution of this research is to present the complete frameworks from error detection to error recovery for fault-tolerant design of VLIW processors. Experience learned from this investigation is that the issues of error detection and error recovery entail considering together. Without taking both issues into account simultaneously, the outcomes may lead to the improper conclusions.

Fault injection and dependability evaluation of fault-tolerant systems

1993 ◽  
Vol 42 (8) ◽  
pp. 913-923 ◽  
Author(s):  
J. Arlat ◽  
A. Costes ◽  
Y. Crouzet ◽  
J.C. Laprie ◽  
D. Powell
Keyword(s):  
Fault Tolerant ◽  
Fault Injection ◽  
Dependability Evaluation ◽  
Fault Tolerant Systems

High-Speed Logic Level Fault Simulation

2011 ◽  
pp. 310-337
Author(s):  
Raimund Ubar ◽  
Sergei Devadze
Keyword(s):  
High Speed ◽  
Fault Tolerant ◽  
Critical Path ◽  
Fault Simulation ◽  
Maximum Size ◽  
Fault Model ◽  
Fault Analysis ◽  
Internal Variables ◽  
Simulation Techniques ◽  
Logic Level

In the first part of the chapter, an introduction to the problem of logic level fault simulation is given together with the overview of existing fault simulation techniques. The remaining part of the chapter describes a new approach to fault simulation based on exact critical path tracing to conduct fault analysis in logic circuits. A circuit topology driven computational model is presented which allows not only to cope with complex structures of nested reconvergent fan-outs but also to carry out the fault reasoning for many test patterns concurrently. To achieve the speed-up of backtracing, the circuit is simulated on higher than traditional gate level. As components of the circuit network, fan-out free regions of maximum size are considered, and they are represented by structurally synthesized BDDs. The latter allow to reduce the number of internal variables in the computation model, and therefore to process the whole circuit faster than on the flat gate-level. The method is explained first, for the stuck-at fault model, and then generalized for an extended class of functional fault model covering the conditional stuck-at and transition faults. The method can be used for simulating permanent faults in combinational circuits, and transient or intermittent faults both in combinational and sequential circuits with the goal of selecting malicious faults for injecting into fault tolerant systems to evaluate their dependability. Experimental results are included to give an idea how efficiently the method works with different fault classes.

Sign in / Sign up

Export Citation Format

Share Document