Using functional fault simulation and the difference fault model to estimate implementation fault coverage

Author(s):  
G.N. Silberman ◽  
I. Spillinger
Author(s):  
Peter Marwedel

AbstractUnfortunately, we cannot rely on designed and possibly already manufactured systems to operate as expected. These systems may have become defective during their use, or their function may have been compromised during the fabrication or their design. The purpose of testing is to verify whether or not an existing embedded/cyber-physical system can be operated as expected. In this chapter, we will present fundamental terms and techniques for testing. There will be a brief introduction to the aims of test pattern generation and their application. We will be introducing terms such as fault model, fault coverage, fault simulation, and fault injection. Also, we will be presenting techniques which improve testability, including the generation of pseudo-random patterns, and signature analysis. It would be beneficial to consider testability issues already during design. In case of fault-tolerant systems, resilience must be verified.


VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 231-242 ◽  
Author(s):  
Sankaran M. Menon ◽  
Yashwant K. Malaiya ◽  
Anura P. Jayasumana

Bipolar Emitter Coupled Logic (ECL) devices can now be fabricated at higher densities and consumes much lower power. Behaviour of simple and complex ECL gates are examined in the presence of physical faults. The effectiveness of the classical stuck-at model in representing physical failures in ECL gates is examined. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. The model may be applicable to other logic families that use logic gates with both true and complementary outputs. A design for testability approach is suggested for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices.


Author(s):  
Mahilchi Milir Vaseekar Kumar ◽  
Spyros Tragoudas ◽  
Sreejit Chakravarty ◽  
Rathish Jayabharathi

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