Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs

2021 ◽  
Author(s):  
Alexandra Zimpeck ◽  
Cristina Meinhardt ◽  
Laurent Artola ◽  
Ricardo Reis
Author(s):  
Alexandra L. Zimpeck ◽  
Cristina Meinhardt ◽  
Laurent Artola ◽  
Guillaume Hubert ◽  
Fernanda L. Kastensmidt ◽  
...  

TAPPI Journal ◽  
2018 ◽  
Vol 17 (05) ◽  
pp. 295-305
Author(s):  
Wesley Gilbert ◽  
Ivan Trush ◽  
Bruce Allison ◽  
Randy Reimer ◽  
Howard Mason

Normal practice in continuous digester operation is to set the production rate through the chip meter speed. This speed is seldom, if ever, adjusted except to change production, and most of the other digester inputs are ratioed to it. The inherent assumption is that constant chip meter speed equates to constant dry mass flow of chips. This is seldom, if ever, true. As a result, the actual production rate, effective alkali (EA)-to-wood and liquor-to-wood ratios may vary substantially from assumed values. This increases process variability and decreases profits. In this report, a new continuous digester production rate control strategy is developed that addresses this shortcoming. A new noncontacting near infrared–based chip moisture sensor is combined with the existing weightometer signal to estimate the actual dry chip mass feedrate entering the digester. The estimated feedrate is then used to implement a novel feedback control strategy that adjusts the chip meter speed to maintain the dry chip feedrate at the target value. The report details the results of applying the new measurements and control strategy to a dual vessel continuous digester.


2018 ◽  
Author(s):  
Oberon Dixon-Luinenburg ◽  
Jordan Fine

Abstract In this paper, we demonstrate a novel nanoprobing approach to establish cause-and-effect relationships between voltage stress and end-of-life performance loss and failure in SRAM cells. A Hyperion II Atomic Force nanoProber was used to examine degradation for five 6T cells on an Intel 14 nm processor. Ten minutes of asymmetrically applied stress at VDD=2 V was used to simulate a ‘0’ bit state held for a long period, subjecting each pullup and pulldown to either VDS or VGS stress. Resultant degradation caused read and hold margins to be reduced by 20% and 5% respectively for the ‘1’ state and 5% and 2% respectively for the ‘0’ state. ION was also reduced, for pulldown and pullup respectively, by 4.5% and 5.4% following VGS stress and 2.6% and 33.8% following VDS stress. Negative read margin failures, soft errors, and read time failures all become more prevalent with these aging symptoms whereas write stability is improved. This new approach enables highly specific root cause analysis and failure prediction for end-of-life in functional on-product SRAM.


2021 ◽  
Vol 2 (2) ◽  
Author(s):  
Muhammad Sheikh Sadi ◽  
Waseem Ahmed ◽  
Jan Jürjens
Keyword(s):  

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