scholarly journals SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

2009 ◽  
Vol 14 (1) ◽  
pp. 1-27 ◽  
Author(s):  
Qiang Xu ◽  
Yubin Zhang ◽  
Krishnendu Chakrabarty
Keyword(s):  
Signal Integrity ◽  
Soc Test ◽  
Embedded Cores ◽  
Architecture Optimization ◽  
Test Architecture

scholarly journals Reconfigured test architecture optimization for TSV-based three-dimensional SoCs

2014 ◽  
Vol 11 (16) ◽  
pp. 20140661-20140661 ◽  
Author(s):  
Kele Shen ◽  
Dong Xiang ◽  
Zhou Jiang
Keyword(s):  
Three Dimensional ◽  
Architecture Optimization ◽  
Test Architecture

Core-Level Compression Technique Selection and SOC Test Architecture Design

2008 ◽  
Author(s):  
Anders Larsson ◽  
Xin Zhang ◽  
Erik Larsson ◽  
Krishnendu Chakrabarty
Keyword(s):  
Core Level ◽  
Architecture Design ◽  
Compression Technique ◽  
Soc Test ◽  
Test Architecture

Research on DFT of Digital Circuits Based on IEEE 1149.1 and Based on IEEE 1500

2014 ◽  
Vol 568-570 ◽  
pp. 1248-1252
Author(s):  
Sheng Jian Chen ◽  
Yong Yu Chen ◽  
Xiao Bing Zhu
Keyword(s):  
Digital Circuits ◽  
Digital Circuit ◽  
Clear Definition ◽  
Embedded Cores ◽  
Ieee 1149.1 ◽  
Definition Of ◽  
Test Architecture ◽  
Related Test

In the field of digital circuit testability design,IEEE 1149.1 standard focuses on System ON board (SOB) test,while the IEEE 1500 standard is for embedded cores test on chip.Although there is a clear definition of two standards, they have a certain relevance.This article will from the process, test principle, test architecture and related test language to analyzethese two standards, concluding that the differences and similarities .Finally, some problems will be pointed out when use the two standards and then make a prospect on the development of the standards.

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