Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint
2012 ◽
Vol 20
(9)
◽
pp. 1621-1633
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2011 ◽
Vol 30
(11)
◽
pp. 1705-1718
◽
2014 ◽
Vol 11
(16)
◽
pp. 20140661-20140661
◽