SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/1455229.1455233 ◽

2009 ◽

Vol 14 (1) ◽

pp. 1-27 ◽

Cited By ~ 5

Author(s):

Qiang Xu ◽

Yubin Zhang ◽

Krishnendu Chakrabarty

Keyword(s):

Signal Integrity ◽

Soc Test ◽

Embedded Cores ◽

SOC test architecture optimization for signal integrity faults on core-external interconnects

2007 44th ACM/IEEE Design Automation Conference ◽

10.1145/1278480.1278651 ◽

2007 ◽

Author(s):

Qiang Xu ◽

Yubin Zhang ◽

Krishnendu Chakrabarty

Keyword(s):

Signal Integrity ◽

Soc Test ◽

Test Architecture Optimization for Post-bond Test and Pre-bond Tests of 3D SoCs Using TAM Reuse

IETE Journal of Research ◽

10.1080/03772063.2020.1870873 ◽

2021 ◽

pp. 1-11

Author(s):

Surajit Kumar Roy ◽

Chandan Giri

Keyword(s):

Bond Tests ◽

Reconfigured test architecture optimization for TSV-based three-dimensional SoCs

IEICE Electronics Express ◽

10.1587/elex.11.20140661 ◽

2014 ◽

Vol 11 (16) ◽

pp. 20140661-20140661 ◽

Cited By ~ 1

Author(s):

Kele Shen ◽

Dong Xiang ◽

Zhou Jiang

Keyword(s):

Three Dimensional ◽

Core-Level Compression Technique Selection and SOC Test Architecture Design

2008 17th Asian Test Symposium ◽

10.1109/ats.2008.71 ◽

2008 ◽

Author(s):

Anders Larsson ◽

Xin Zhang ◽

Erik Larsson ◽

Krishnendu Chakrabarty

Keyword(s):

Core Level ◽

Architecture Design ◽

Compression Technique ◽

Soc Test ◽

Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain

IEEE International Conference on Test, 2005. ◽

10.1109/test.2005.1584022 ◽

2006 ◽

Cited By ~ 19

Author(s):

T. Waayers ◽

R. Morren ◽

R. Grandi

Keyword(s):

Soc Test ◽

Definition Of ◽

Test-Architecture Optimization and Test Scheduling

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_8 ◽

2013 ◽

pp. 181-237

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

Keyword(s):

Test Scheduling ◽

Test-architecture optimization and test scheduling for SOCs with core-level expansion of compressed test patterns

2008 Design, Automation and Test in Europe ◽

10.1145/1403375.1403422 ◽

2008 ◽

Author(s):

Anders Larsson ◽

Erik Larsson ◽

Krishnendu Chakrabarty ◽

Petru Eles ◽

Zebo Peng

Keyword(s):

Core Level ◽

Test Scheduling ◽

Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2008.917974 ◽

2008 ◽

Vol 27 (5) ◽

pp. 973-977 ◽

Cited By ~ 21

Author(s):

S. Samii ◽

M. Selkala ◽

E. Larsson ◽

K. Chakrabarty ◽

Zebo Peng

Keyword(s):

Architecture Design ◽

Power Modeling ◽

Test Power ◽

Soc Test ◽

2008 International Conference on Electronic Packaging Technology & High Density Packaging ◽

The optimization of hierarchical SOC test architecture to reduce test time

10.1109/icept.2008.4607101 ◽

2008 ◽

Cited By ~ 3

Author(s):

Xu Chuan-pei ◽

Dai Kui

Keyword(s):

Test Time ◽

Soc Test ◽