Family-Based Model Checking Without a Family-Based Model Checker

2015 ◽  
pp. 282-299 ◽  
Author(s):  
Aleksandar S. Dimovski ◽  
Ahmad Salim Al-Sibahi ◽  
Claus Brabrand ◽  
Andrzej Wąsowski
Keyword(s):  
Model Checking ◽  
Model Checker ◽  
Family Based

scholarly journals Verification and Strategy Synthesis for Coalition Announcement Logic

2021 ◽  
Author(s):  
Natasha Alechina ◽  
Hans van Ditmarsch ◽  
Rustam Galimullin ◽  
Tuo Wang
Keyword(s):  
Model Checking ◽  
Proof Of Concept ◽  
Model Checker ◽  
Complete Model ◽  
Concept Model ◽  
The Family ◽  
Winning Strategies ◽  
Epistemic Goals

AbstractCoalition announcement logic (CAL) is one of the family of the logics of quantified announcements. It allows us to reason about what a coalition of agents can achieve by making announcements in the setting where the anti-coalition may have an announcement of their own to preclude the former from reaching its epistemic goals. In this paper, we describe a PSPACE-complete model checking algorithm for CAL that produces winning strategies for coalitions. The algorithm is implemented in a proof-of-concept model checker.

scholarly journals Model Checking Temporal Epistemic Logic under Bounded Recall

2020 ◽  
Vol 34 (05) ◽  
pp. 7071-7078
Author(s):  
Francesco Belardinelli ◽  
Alessio Lomuscio ◽  
Emily Yu
Keyword(s):  
Model Checking ◽  
Incomplete Information ◽  
Epistemic Logic ◽  
Upper Bounds ◽  
Experimental Results ◽  
Model Checker ◽  
Multi Agent Systems ◽  
Agent Systems ◽  
Multi Agent ◽  
Bounded Recall

We study the problem of verifying multi-agent systems under the assumption of bounded recall. We introduce the logic CTLKBR, a bounded-recall variant of the temporal-epistemic logic CTLK. We define and study the model checking problem against CTLK specifications under incomplete information and bounded recall and present complexity upper bounds. We present an extension of the BDD-based model checker MCMAS implementing model checking under bounded recall semantics and discuss the experimental results obtained.

SUPPORTING FORMAL VERIFICATION OF DIMA MULTI-AGENTS MODELS: TOWARDS A FRAMEWORK BASED ON MAUDE MODEL CHECKING

2008 ◽  
Vol 18 (07) ◽  
pp. 853-875 ◽  
Author(s):  
NOURA BOUDIAF ◽  
FARID MOKHATI ◽  
MOURAD BADRI
Keyword(s):  
Model Checking ◽  
Development Process ◽  
Formal Semantics ◽  
Concurrent Systems ◽  
Model Checker ◽  
Rewriting Logic ◽  
Generic Framework ◽  
Systems Quality ◽  
Verification Techniques ◽  
Multi Agents

Model Checking based verification techniques represent an important issue in the field of concurrent systems quality assurance. The lack of formal semantics in the existing formalisms describing multi-agents models combined with multi-agents systems complexity are sources of several problems during their development process. The Maude language, based on rewriting logic, offers a rich notation supporting formal specification and implementation of concurrent systems. In addition to its modeling capacity, the Maude environment integrates a Model Checker based on Linear Temporal Logic (LTL) for distributed systems verification. In this paper, we present a formal and generic framework (DIMA-Maude) supporting formal description and verification of DIMA multi-agents models.

Efficient Bounded Model Checking for LTL

2013 ◽  
Vol 380-384 ◽  
pp. 1239-1242
Author(s):  
Rui Wang ◽  
Xian Jin Fu
Keyword(s):  
Model Checking ◽  
Efficient Method ◽  
Bounded Model Checking ◽  
Specification Languages ◽  
Model Checker ◽  
System Designs

Bounded Model Checking is an efficient method of finding bugs in system designs. LTL is one of the most frequently used specification languages in model checking. In this paper, We present an linearization encoding for LTL bounded model checking. We use the incremental SAT technology to solve the BMC problem. We implement the new encoding in NuSMV model checker.

scholarly journals Dartagnan: Leveraging Compiler Optimizations and the Price of Precision (Competition Contribution)

2021 ◽  
pp. 428-432
Author(s):  
Hernán Ponce-de-León ◽  
Thomas Haas ◽  
Roland Meyer
Keyword(s):  
Model Checking ◽  
Bounded Model Checking ◽  
Model Checker ◽  
Compiler Optimizations ◽  
Sequential Programs ◽  
Input Program ◽  
Order Of Magnitude ◽  
Speed Up ◽  
First Time ◽  
Bitwise Operations

AbstractWe describe the new features of the bounded model checker Dartagnan for SV-COMP ’21. We participate, for the first time, in the ReachSafety category on the verification of sequential programs. In some of these verification tasks, bugs only show up after many loop iterations, which is a challenge for bounded model checking. We address the challenge by simplifying the structure of the input program while preserving its semantics. For simplification, we leverage common compiler optimizations, which we get for free by using LLVM. Yet, there is a price to pay. Compiler optimizations may introduce bitwise operations, which require bit-precise reasoning. We evaluated an SMT encoding based on the theory of integers + bit conversions against one based on the theory of bit-vectors and found that the latter yields better performance. Compared to the unoptimized version of Dartagnan, the combination of compiler optimizations and bit-vectors yields a speed-up of an order of magnitude on average.

scholarly journals Model-Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 1057
Author(s):  
Gianpiero Cabodi ◽  
Paolo Camurati ◽  
Fabrizio Finocchiaro ◽  
Danilo Vendraminetto
Keyword(s):  
Model Checking ◽  
Formal Verification ◽  
High Performance ◽  
State Of The Art ◽  
Realistic Model ◽  
Bounded Model Checking ◽  
Sensitive Information ◽  
Model Checker ◽  
Verification Process ◽  
Verification Techniques

Spectre and Meltdown attacks in modern microprocessors represent a new class of attacks that have been difficult to deal with. They underline vulnerabilities in hardware design that have been going unnoticed for years. This shows the weakness of the state-of-the-art verification process and design practices. These attacks are OS-independent, and they do not exploit any software vulnerabilities. Moreover, they violate all security assumptions ensured by standard security procedures, (e.g., address space isolation), and, as a result, every security mechanism built upon these guarantees. These vulnerabilities allow the attacker to retrieve leaked data without accessing the secret directly. Indeed, they make use of covert channels, which are mechanisms of hidden communication that convey sensitive information without any visible information flow between the malicious party and the victim. The root cause of this type of side-channel attacks lies within the speculative and out-of-order execution of modern high-performance microarchitectures. Since modern processors are hard to verify with standard formal verification techniques, we present a methodology that shows how to transform a realistic model of a speculative and out-of-order processor into an abstract one. Following related formal verification approaches, we simplify the model under consideration by abstraction and refinement steps. We also present an approach to formally verify the abstract model using a standard model checker. The theoretical flow, reliant on established formal verification results, is introduced and a sketch of proof is provided for soundness and correctness. Finally, we demonstrate the feasibility of our approach, by applying it on a pipelined DLX RISC-inspired processor architecture. We show preliminary experimental results to support our claim, performing Bounded Model-Checking with a state-of-the-art model checker.

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