On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study

2017 ◽  
pp. 39-57
Author(s):  
Vladimir Herdt ◽  
Hoang M. Le ◽  
Daniel Große ◽  
Rolf Drechsler
Keyword(s):  
Correspondence Analysis ◽  
Fault Localization

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Correspondence analysis of repair data: a case study for electric cable shovels

2008 ◽  
Vol 35 (8) ◽  
pp. 901-908 ◽  
Author(s):  
Sermin Elevli ◽  
Nevin Uzgören ◽  
Birol Elevli
Keyword(s):  
Correspondence Analysis ◽  
Electric Cable

Case Study—Lock-in Thermography Application in Failure Analysis of a System Level DC-DC μModule Regulator

2017 ◽  
Author(s):  
Vikash Kumar ◽  
Devraj Karthikeyan
Keyword(s):  
Heat Source ◽  
Failure Analysis ◽  
Case Studies ◽  
Fault Localization ◽  
System Level ◽  
Thermal Failure ◽  
Analysis Process ◽  
Lock In

Abstract Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator

A Case Study for Mutation-based Fault Localization for FBD Programs

2016 ◽  
Vol 22 (3) ◽  
pp. 145-150
Author(s):  
Donghwan Shin ◽  
Junho Kim ◽  
Wonkyung Yun ◽  
Eunkyoung Jee ◽  
Doo-Hwan Bae
Keyword(s):  
Fault Localization
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