A Low Power Branch Predictor to Selectively Access the BTB

Author(s):  
Sung Woo Chung ◽  
Sung Bae Park
Keyword(s):  
2006 ◽  
Vol 2 (3) ◽  
pp. 333-341 ◽  
Author(s):  
Kaveh Aasaraai ◽  
Amirali Baniasadi
Keyword(s):  

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 292
Author(s):  
Wenheng Ma ◽  
Qiao Cheng ◽  
Yudi Gao ◽  
Lan Xu ◽  
Ningmei Yu

Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 μW, 59.7 μW and 71.1 μW. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.


Author(s):  
Rahul Sarpeshkar
Keyword(s):  

2018 ◽  
Vol 49 (1) ◽  
pp. 47-62 ◽  
Author(s):  
Petra C. Schmid

Abstract. Power facilitates goal pursuit, but how does power affect the way people respond to conflict between their multiple goals? Our results showed that higher trait power was associated with reduced experience of conflict in scenarios describing multiple goals (Study 1) and between personal goals (Study 2). Moreover, manipulated low power increased individuals’ experience of goal conflict relative to high power and a control condition (Studies 3 and 4), with the consequence that they planned to invest less into the pursuit of their goals in the future. With its focus on multiple goals and individuals’ experiences during goal pursuit rather than objective performance, the present research uses new angles to examine power effects on goal pursuit.


2019 ◽  
Vol 117 (2) ◽  
pp. 338-363 ◽  
Author(s):  
Emily J. Cross ◽  
Nickola C. Overall ◽  
Rachel S. T. Low ◽  
James K. McNulty

2004 ◽  
Vol 18 (3) ◽  
pp. 37
Author(s):  
J. Frenkil
Keyword(s):  

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