scholarly journals An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 292
Author(s):  
Wenheng Ma ◽  
Qiao Cheng ◽  
Yudi Gao ◽  
Lan Xu ◽  
Ningmei Yu
Keyword(s):  
Energy Efficiency ◽  
Low Power ◽  
Normal Mode ◽  
High Performance ◽  
Mode Switching ◽  
Peak Performance ◽  
Embedded Processors ◽  
Ultra Low Power ◽  
Branch Predictor ◽  
Power Mode

Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 μW, 59.7 μW and 71.1 μW. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.

NTB branch predictor: dynamic branch predictor for high-performance embedded processors

2014 ◽  
Vol 72 (5) ◽  
pp. 1679-1693 ◽  
Author(s):  
Cong Thuan Do ◽  
Hong Jun Choi ◽  
Dong Oh Son ◽  
Jong Myon Kim ◽  
Cheol Hong Kim
Keyword(s):  
High Performance ◽  
Embedded Processors ◽  
Branch Predictor

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

scholarly journals Design and Implementation of Smart Non-Invasive Bone Conduction Ear-Plug System

2018 ◽  
Vol 9 (2) ◽  
pp. 249
Author(s):  
Ravichandran G ◽  
M Krishnamurthy
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
High Performance ◽  
Bone Conduction ◽  
Ultra Low Power ◽  
Audio Processing ◽  
Activity Tracker ◽  
Non Invasive ◽  
Run Up ◽  
Music Player

<p>The project aim is to design a smart earplug system integrated with non-invasive bone conduction technique which is capable of doing some advanced audio processing to provide voice enhancing, noise filtered audio for the hearing impaired people [2]. The system is also designed to work as an embedded music player, a life activity tracker and a Smartphone companion. It can even read the SMS that is just received on your smartphone into your ear. This project needs a very low power microcontroller but with high-performance signal processing requirements. STM32L476 from STMicroelectronics meets this needs and thus chosen as the main MCU. It is an ultra-low power ARM Cortex-M4 based microcontroller that can run up to 80MHz.  It has got 1MB of Flash memory and 128 KB RAM.</p>

Optimal design for a high performance H-JLTFET using HfO2 as a gate dielectric for ultra low power applications

RSC Advances ◽  
2014 ◽  
Vol 4 (43) ◽  
pp. 22803-22807 ◽  
Author(s):  
Pranav Kumar Asthana ◽  
Bahniman Ghosh ◽  
Shiromani Bal Mukund Rahi ◽  
Yogesh Goswami
Keyword(s):  
Optimal Design ◽  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Ultra Low Power ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor using HfO2 as a gate dielectric.

scholarly journals Level Converters for Ultra Low Power IoT Applications

2018 ◽  
Vol 7 (2.16) ◽  
pp. 19
Author(s):  
T Yugendra Chary ◽  
S Anitha ◽  
M Alamillo ◽  
Ameet Chavan
Keyword(s):  
Energy Efficiency ◽  
Low Power ◽  
Slight Reduction ◽  
Dramatic Improvement ◽  
Modest Improvement ◽  
Ultra Low Power ◽  
Iot Applications ◽  
Communication Devices ◽  
And Performance ◽  
Level Converter

For efficient ultra-low power IoT applications, working with various communication devices and sensors which operating voltages  from subthreshold to superthreshold levels which requires wide variety of robust level converters for signal interfacing with low power dissipation. This paper proposes two topologies of level converter circuits that offer dramatic improvement in power and performance when compared to the existing level converters that shift signals from sub to super threshold levels for IoT applications. At 250 mV, the first proposed circuit - a modification of a tradition al current mirror level converter - offers the best energy efficiency with approximately seven times less energy consumption per operation than the existing design, but suffers from a slight reduction in performance.  However, a second proposed circuit - based on a two-stage level converter - at the same voltage enhances performance by several orders of magnitude while still maintaining a modest improvement in energy efficiency.  The Energy Delay Products (EDP) of the two proposed designs are equivalent and are approximately four times better than the best existing design.  Consequently, the two circuit options either optimizes power or performance with improved overall EDP.  

scholarly journals A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Future Generation ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Ultra Low Power

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

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