An Area Efficient Design of Warped Filters

2018 ◽  
pp. 189-200
Author(s):  
Kruttika Golwelker ◽  
Ritu Kumari ◽  
T. Vigneswaran
Keyword(s):  
Efficient Design ◽  
Area Efficient

A 0.039 mm$^2$ Inverter-Based 1.82 mW 68.6$~$ dB-SNDR 10 MHz-BW CT-$\Sigma\Delta$ -ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques

2014 ◽  
Vol 49 (7) ◽  
pp. 1548-1560 ◽  
Author(s):  
Sebastian Zeller ◽  
Christian Muenker ◽  
Robert Weigel ◽  
Ussmueller Ussmueller
Keyword(s):  
Efficient Design ◽  
Sigma Delta ◽  
Area Efficient ◽  
Design Techniques

scholarly journals An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers

2016 ◽  
Vol 13 (11) ◽  
pp. 20160138-20160138 ◽  
Author(s):  
Yang Jinjiang ◽  
Ge Wei ◽  
Cao Peng ◽  
Yang Jun
Keyword(s):  
Parallel Implementation ◽  
Block Ciphers ◽  
Efficient Design ◽  
Area Efficient

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

2016 ◽  
Vol 26 (02) ◽  
pp. 1750030 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Cmos Technology ◽  
Two Dimensional ◽  
Efficient Design ◽  
Parallel Multiplier ◽  
Power Delay Product ◽  
Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

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