A Power Efficient Hardware Implementation of the IF Neuron Model

2018 ◽  
pp. 140-154
Author(s):  
Shuquan Wang ◽  
Shasha Guo ◽  
Lei Wang ◽  
Nan Li ◽  
Zikai Nie ◽  
...  
Keyword(s):  
Neuron Model ◽  
Hardware Implementation ◽  
Power Efficient

scholarly journals Smooth Nonlinear Fitting Scheme for Analog Multiplierless Implementation of Hindmarsh-Rose Neuron Model

2021 ◽  
Author(s):  
Jianming Cai ◽  
Han Bao ◽  
Quan Xu ◽  
Zhongyun Hua ◽  
Bocheng Bao
Keyword(s):  
Large Scale ◽  
Neuron Model ◽  
Hardware Implementation ◽  
Three Dimensional ◽  
Two Dimensional ◽  
Implementation Cost ◽  
Hyperbolic Tangent ◽  
Nonlinear Fitting ◽  
Chaotic Bursting ◽  
Electrical Activities

Abstract The Hindmarsh-Rose (HR) neuron model is built to describe the neuron electrical activities. Due to the polynomial nonlinearities, multipliers are required to implement the HR neuron model in analog. In order to avoid the multipliers, this brief presents a novel smooth nonlinear fitting scheme. We first construct two nonlinear fitting functions using the composite hyperbolic tangent functions and then implement an analog multiplierless circuit for the two-dimensional (2D) or three- dimensional (3D) HR neuron model. To exhibit the nonlinear fitting effects, numerical simulations and hardware experiments for the fitted HR neuron model are provided successively. The results show that the fitted HR neuron model with analog multiplierless circuit can display different operation patterns of resting, periodic spiking, and periodic/chaotic bursting, entirely behaving like the original HR neuron model. The analog multiplierless circuit has the advantage of low implementation cost and thereby it might be suitable for the hardware implementation of large-scale neural networks.

Web-enabled Neuron Model Hardware Implementation and Testing

2015 ◽  
Author(s):  
Fearghal Morgan ◽  
Finn Krewer ◽  
Frank Callaly ◽  
Aedan Coffey ◽  
Brian Mc Ginley
Keyword(s):  
Neuron Model ◽  
Hardware Implementation

A Low Power CORDIC-Based Hardware Implementation of Izhikevich Neuron Model

2018 ◽  
Author(s):  
Abdelrahim Elnabawy ◽  
Hussien Abdelmohsen ◽  
Moatasem Moustafa ◽  
Mostafa Elbediwy ◽  
Amr Helmy ◽  
...  
Keyword(s):  
Low Power ◽  
Neuron Model ◽  
Hardware Implementation ◽  
Izhikevich Neuron Model

Digital hardware implementation of a stochastic two-dimensional neuron model

2016 ◽  
Vol 110 (4) ◽  
pp. 409-416 ◽  
Author(s):  
F. Grassia ◽  
T. Kohno ◽  
T. Levi
Keyword(s):  
Neuron Model ◽  
Hardware Implementation ◽  
Two Dimensional ◽  
Digital Hardware

scholarly journals Using Pruning and Truncation for Power-Efficient 2-D Approximate Tchebichef Transform Hardware Architecture

2018 ◽  
Vol 13 (1) ◽  
pp. 1-6
Author(s):  
Guilherme Paim ◽  
Leandro M. G. Rocha ◽  
Gustavo M. Santana ◽  
Leonardo B. Soares ◽  
Eduardo A. C. Da Costa ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Hardware Implementation ◽  
State Of The Art ◽  
Power Efficient ◽  
Power Extraction ◽  
Standard Cells ◽  
Discrete Transforms ◽  
Intensive Use ◽  
Discrete Tchebichef Transform ◽  
Hardware Designs

Due to the intensive use of discrete transforms in pic-ture coding, the search for fast and power-efficient approaches for their hardware implementation has gained importance. The DTT (Discrete Tchebichef Transform) represents a discrete class of the Chebyshev orthogonal polynomials, and it is an al-ternative for the DCT (Discrete Cosine Transform), commonly used in picture coding. In this work, we propose a new approx-imation for the integer DTT, with better quality and power-ef-ficiency by exploring truncation and pruning. The principal idea is reduce the values of coefficients to fractions enables trun-cation by shifts in the internal transform calculations and lead to lower values for the non-diagonal residues, which reduces non-orthogonality. We have also selectively pruned the rows of the state-of-the-art approximate DTT matrix. The approximate DTT architectures were synthesized for ASIC in Cadence RTL Compiler tool using a realistic power extraction methodology considering real-inputs vectors and the delays, with the Nangate 45 nm standard cells library. The synthesis results show that the proposed-pruned approximate DTT hardwired solution in-creases the maximum frequency about 10.78%, minimize cells area by 50.2%, with savings up to 55.9% of power dissipation with more compression ratio and less quality losses in the com-pressed image, when compared with state-of-the-art approxi-mate DTT hardware designs.

Hardware Implementation Of Iris Matching

2012 ◽  
Vol 1 (6) ◽  
pp. 46-48
Author(s):  
Bethuna Bethuna ◽  
Keyword(s):  
Hardware Implementation

An Improvement of Rate-Distortion Optimized Quantization Process and its Hardware Implementation

2015 ◽  
Vol 135 (11) ◽  
pp. 1299-1306
Author(s):  
Genki Moriguchi ◽  
Takashi Kambe ◽  
Gen Fujita ◽  
Hajime Sawano
Keyword(s):  
Hardware Implementation ◽  
Rate Distortion
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