Modified quantum frequency standard on Hg-199 ions

The world around us depends on devices capable of producing or maintaining a signal with an extreme precision. Quantum frequency standards are the answer to this problem. This article presents a modified version of newly developed quantum frequency standard based on trapping Hg-199 ions by magnetic field. The new prototype was developed a while ago and now it was modified due to algorithm improvements and renewed digital hardware, analog and digital circuitry being reordered. Results for Allan deviation show 3 % improvement for long-term frequency stability and more than 5 % for short-term stability

FPGA REALIZATION OF COMPLEX LOGISTIC MAP FRACTAL BEHAVIOR

This paper studies the capability of digital architecture to mimic fractal behavior. As chaotic attractors realized digitally had opened many tracks, digital designs mimicking fractals may ultimately achieve the same. This study is based on a complex single-dimensional discrete chaotic system known as the generalized positive logistic map. The fractals realized from this system are linked to the results of the mathematical analysis to understand the fractal behavior with different variations. A digital hardware architecture manifesting the fractal behavior is achieved on FPGA, showing a fractal entity experimentally. With this digital realization, it is hoped that fractals can follow the example of chaotic attractors digital applications.

Digital Hardware for Peer Assessment in K-12 Schools and Universities

Digital peer assessment (PA) is an arrangement for learners to consider and specify the level, value, or quality of a product or the performance of other equal-status learners, using computers, tablets, mobiles or other devices, and the internet. Digital PA is of increasing relevance as more educational establishments are moving toward online or blended learning. It has been widely used for some time, not only in elementary (primary) and high (secondary) schools but also in higher education. In this article, the purposes of PA are considered. Then, questions of effectiveness are briefly discussed. Then, the majority of the article describes in general terms how to do it. A review is offered for variations in types of PA and the underpinning theory, both of which have practical implications, irrespective of whether the PA is digital or face-to-face. Then, the use of different kinds of digital hardware in different kinds of PA will be considered. After this, the social and emotional aspects of digital PA are considered. As the contexts are so different, differences between primary school, high school, and higher education are reviewed. A conclusion summarises the strengths and weaknesses of digital PA, which can certainly be effective as a teaching and learning method and enhance student communication, problem-solving, and self-confidence.

The Notification Oriented Paradigm Language to Digital Hardware as an Intuitive High-level Synthesis Tool

The parallelism allowed by FPGAs has attracted attention for knowing applications that need processing power. However, the need for specific and very technical development language has not stimulate its broad use. As an alternative, there are High-level Synthesis Languages (HSL), which allow less complicated FPGA use. However, they do not tend to take full advantage of the FPGA technology. Therefore, another alternative was developed, based on the Notification Oriented Paradigm (NOP), called NOP for Digital Hardware (NOP-DH). NOP allows development in high level with its rule-oriented language called NOPL. Its entity decoupling, parallelism, and redundancy avoidance are useful for best performance. In turn, the NOP-DH brings NOP for the FPGA context with the benefits observed in software but enhanced by hardware nature. This paper reviews the NOPL for NOP-DH (NOPL-DH) that aims high level programming for FPGA. The paper proposes the NOPL-DH test by independent developers, by developing a monitoring device for a box transporting bidirectional conveyer. As a result, NOPL-DH allowed high-level development under the NOP-DH structure in an FPGA, without the need for technical knowledge and, still, maintaining and exploring the NOP properties in FPGA

Characteristics of MPSoC Based On Dual Feedback Edge Triggered Flip Flop

With the persistent scaling of semiconductor technology, the embedded multi-processor platforms lifetime reliability has been the primary concern for the industry. The advancements in technology permit several microprocessors integration, dedicated digital hardware, and at times mixed-signal circuits on a single silicon die, specifically multi-processor system-on-a-chip (MPSoC). In this paper, the design and analysis of CMOS based MPSoC is made. A CMOS based MPSoC is designed with 45nm technology. In this design, ADC converter is used in which 10-bit data is given as input, and are converted into digital data. A double feedback edge triggered flip flop is designed. The implementation of flip flop, based on both feedback and triggering process, is more effective in the elimination of error occurrence. Power Gating (PG) technique is proposed which exploits the stacking effect to achieve high energy efficiency. Binary controlled stacked SRAM cell, based on a parallel cross-coupling feedback controller, is implemented to reduce the leakage loss and ground bouncing noise. An inverter, based on NMOS and CMOS, is used for the inverting process. The input voltage of 5v is given and is varied. Then, a 2-bit counter is employed, which is responsible for counting down or counting up. The counter should count down if the signal is high. The counter should count up, if the signal is low. Thus, this design will be helpful in the implementation of compact processing system which may also be employed for many real-time applications where there is a need of compact device. The benefits of this multi processors integration will be helpful in speeding the process thereby reducing the leakage power loss, power consumption, delay factor and so on. The analysis of performance is carried out using CMOS based Tanner EDA, and the outcomes are represented.

High throughput resource efficient reconfigurable interleaver for MIMO WLAN application

Demand for high-speed wireless broadband internet service is ever increasing. Multiple-input-multiple-output (MIMO) Wireless LAN (WLAN) is becoming a promising solution for such high-speed internet service requirements. This paper proposes a novel algorithm to efficiently model the address generation circuitry of the MIMO WLAN interleaver. The interleaver used in the MIMO WLAN transceiver has three permutation steps involving floor function whose hardware implementation is the most challenging task due to the absence of corresponding digital hardware. In this work, we propose an algorithm with a mathematical background for the address generator, eliminating the need for floor function. The algorithm is converted into digital hardware for implementation on the reconfigurable FPGA platform. Hardware structure for the complete interleaver, including the read address generator and memory module, is designed and modeled in VHDL using Xilinx Integrated Software Environment (ISE) utilizing embedded memory and DSP blocks of Spartan 6 FPGA. The functionality of the proposed algorithm is verified through exhaustive software simulation using ModelSim software. Hardware testing is carried out on Zynq 7000 FPGA using Virtual Input Output (VIO) and Integrated Logic Analyzer (ILA) core. Comparisons with few recent similar works, including the conventional Look-Up Table (LUT) based technique, show the superiority of our proposed design in terms of maximum improvement in operating frequency by 196.83%, maximum reduction in power consumption by 74.27%, and reduction of memory occupancy by 88.9%. In the case of throughput, our design can deliver 8.35 times higher compared to IEEE 802.11n requirement.

Streaming Algorithms for Subspace Analysis: an Edge- and Hardware-oriented review

Subspace analysis is a basic tool for coping with high-dimensional data and is becoming a fundamental step in early processing of many signals elaboration tasks. Nowadays trend of collecting huge quantities of usually very redundant data by means of decentralized systems suggests these techniques be deployed as close as possible to the data sources. Regrettably, despite its conceptual simplicity, subspace analysis is ultimately equivalent to eigenspace computation and brings along non-negligible computational and memory requirements. To make this fit into typical systems operating at the edge, specialized streaming algorithms have been recently devised that we here classify and review giving them a coherent description, highlighting features and analogies, and easing comparisons. Implementation of these methods is also tested on a common edge digital hardware platform to estimate not only abstract functional and complexity features, but also more practical running times and memory footprints on which compliance with real-world applications hinges.

Streaming Algorithms for Subspace Analysis: an Edge- and Hardware-oriented review

Subspace analysis is a basic tool for coping with high-dimensional data and is becoming a fundamental step in early processing of many signals elaboration tasks. Nowadays trend of collecting huge quantities of usually very redundant data by means of decentralized systems suggests these techniques be deployed as close as possible to the data sources. Regrettably, despite its conceptual simplicity, subspace analysis is ultimately equivalent to eigenspace computation and brings along non-negligible computational and memory requirements. To make this fit into typical systems operating at the edge, specialized streaming algorithms have been recently devised that we here classify and review giving them a coherent description, highlighting features and analogies, and easing comparisons. Implementation of these methods is also tested on a common edge digital hardware platform to estimate not only abstract functional and complexity features, but also more practical running times and memory footprints on which compliance with real-world applications hinges.

New Models for Solving Time-Varying LU Decomposition by Using ZNN Method and ZeaD Formulas

In this paper, by employing the Zhang neural network (ZNN) method, an effective continuous-time LU decomposition (CTLUD) model is firstly proposed, analyzed, and investigated for solving the time-varying LU decomposition problem. Then, for the convenience of digital hardware realization, this paper proposes three discrete-time models by using Euler, 4-instant Zhang et al. discretization (ZeaD), and 8-instant ZeaD formulas to discretize the proposed CTLUD model, respectively. Furthermore, the proposed models are used to perform the LU decomposition of three time-varying matrices with different dimensions. Results indicate that the proposed models are effective for solving the time-varying LU decomposition problem, and the 8-instant ZeaD LU decomposition model has the highest precision among the three discrete-time models.