Design of 2-D Parity Generation for Burst Error Detection

Author(s):  
Vivek Kumar Srivastava ◽  
Shreya ◽  
Amrindra Pal ◽  
Sandeep Sharma
Keyword(s):  
Author(s):  
Biagio Buccimazza ◽  
Bal Kishan Dass ◽  
Sapna Jain

2019 ◽  
Vol 8 (2S8) ◽  
pp. 1948-1952

The developments in IC technology and rapid increase of transistor densities and scaling factor, the use of ECC’s acquired prominence. Multiple bit errors in memories due to technology scaling demands advanced error correction codes. SEC-DEC, DEC, burst error detection, Golay code, Reed Solmon codes etc. have much decoding complexity and latency. The above drawbacks can be reduced with OLS codes. OLS codes with majority logic decoding technique, modular construction and simple decoding mechanisms it enables low delay improvements. MBU’S can be addressed using OLS-MLD codes. This paper presents a detail study of developments in multibit ECC’s using OLS-MLD mechanism


2007 ◽  
Vol 14 (02) ◽  
pp. 341-350 ◽  
Author(s):  
Sapna Jain ◽  
K. P. Shum

Lee weight is more appropriate for some practical situations than Hamming weight as it takes into account the magnitude of each digit of the word. In this paper, we obtain a sufficient bound over the number of parity check digits for codes detecting burst errors and also for codes correcting burst errors with Lee weight.


Author(s):  
Luis-J. Saiz-Adalid ◽  
Pedro Gil ◽  
J.-Carlos Baraza-Calvo ◽  
Juan-Carlos Ruiz ◽  
Daniel Gil-Tomas ◽  
...  

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