Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects

Occurrence of bit error is more when communication takes place in System on chip environment. By employing proper error detection and correction codes the bit error rate can be considerably reduced in On-chip communication. As System on chip involves heterogeneous system the efficiency of communication is improved when reconfigurable multiple coding schemes are preferred. Depending upon the requirements for various subsystem the correct code has to be selected. Due to the variations in input demands based on various subsystems the proper selection of codes become fuzzy in nature. In this paper Fuzzy Controller is designed to select the correct coding scheme. Inputs are given to the fuzzy controller based on the application demand of the user. The input parameters are minimum bit error rate, computational complexity and correlation level of the input data. Fuzzy Controller employs three membership functions and 27 rules to select the appropriate coding scheme. The selected coding scheme should be communicated at the proper time to the decoder. To enable the decoding process selected coding scheme is communicated effectively by using less overhead frame format. To verify the functionality of fuzzy controller random input data sets are used for testing.

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High-density-burst error detection

Journal of Discrete Mathematical Sciences and Cryptography ◽

10.1080/09720529.2004.10697984 ◽

2004 ◽

Vol 7 (1) ◽

pp. 5-21

Author(s):

Biagio Buccimazza ◽

Bal Kishan Dass ◽

Sapna Jain

Keyword(s):

Error Detection ◽

High Density ◽

Burst Error

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Low Cost Concurrent Error Detection for On-Chip Memory Based Embedded Processors

2011 IFIP 9th International Conference on Embedded and Ubiquitous Computing ◽

10.1109/euc.2011.47 ◽

2011 ◽

Cited By ~ 2

Author(s):

Faramarz Khosravi ◽

Hamed Farbeh ◽

Mahdi Fazeli ◽

Seyed Ghassem Miremadi

Keyword(s):

Error Detection ◽

Low Cost ◽

Embedded Processors ◽

Concurrent Error Detection ◽

On Chip

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Error Correction Codes Derived from Orthogonal Latin Square Codes

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.b1205.0882s819 ◽

2019 ◽

Vol 8 (2S8) ◽

pp. 1948-1952

Keyword(s):

Error Correction ◽

Error Detection ◽

Latin Square ◽

Error Correction Codes ◽

Modular Construction ◽

Golay Code ◽

Technology Scaling ◽

Burst Error ◽

Majority Logic Decoding ◽

Ic Technology

The developments in IC technology and rapid increase of transistor densities and scaling factor, the use of ECC’s acquired prominence. Multiple bit errors in memories due to technology scaling demands advanced error correction codes. SEC-DEC, DEC, burst error detection, Golay code, Reed Solmon codes etc. have much decoding complexity and latency. The above drawbacks can be reduced with OLS codes. OLS codes with majority logic decoding technique, modular construction and simple decoding mechanisms it enables low delay improvements. MBU’S can be addressed using OLS-MLD codes. This paper presents a detail study of developments in multibit ECC’s using OLS-MLD mechanism

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