An Accurate CMOS Interface Small Capacitance Variation Sensing Circuit for Capacitive Sensor Applications

2017 ◽  
Vol 36 (12) ◽  
pp. 4908-4918
Author(s):  
H. G. Momen ◽  
M. Yazgi ◽  
R. Kopru ◽  
A. Naderi Saatlo
Sensors ◽  
2021 ◽  
Vol 21 (17) ◽  
pp. 5958
Author(s):  
Andrea G. Martinez-Lopez ◽  
David E. Guzmán-Caballero ◽  
Israel Mejia ◽  
Julio C. Tinoco

The development of silicon-based sensor devices has enabled the possibility to pursue novel integrated smart sensor technologies. Under this scenario, capacitive sensor devices are one viable option for implementing different kinds of applications. In this paper, an interdigitated coplanar capacitive device fabricated over a silicon substrate is presented and its potential use as liquid sensor is demonstrated. Additionally, a detailed capacitance model, which includes the parasitic capacitances introduced by the silicon substrate, was developed. The capacitance model has been theoretically validated through finite-element simulations as well as experimentally by comparison with fabricated devices. A polydimethylsiloxane mold has been fabricated and bonded to the sensor device with the aim of defining a cavity to collect the liquid sample into the device’s active region. The active capacitance component correlates to the electric field coupling between adjacent metal lines. Therefore, any change to the dielectric constant of the medium above the coplanar metal lines will produce a change to the device capacitance. Finally, the main guidelines for device performance improvement are depicted.


Author(s):  
Ajay AP ◽  
KN Bhat ◽  
Navakanta Bhat ◽  
SM Kulkarni

The paper considers modeling and analysis of a square and circular diaphragm Suspended Gate MOSFET based pressure sensor using COMSOL Multiphysics. Two structures, one a square with an n-channel MOSFET at the center and the second a circle with a p-channel MOSFET at the edge of the diaphragm were simulated. The piezoresistance effect of the channel and capacitance variation due to the suspended gate have been exploited in designing the sensor. The combined effect of the two has not been reported in literature so far and this is the first attempt at combining the two effects for transduction. Channel is modelled separately as an equivalent piezoresistor and the capacitance variation is also simulated in COMSOL. The MOSFET characteristics in the unstrained and strained conditions are modelled using COMSOL and MATLAB. The MOSFETs are operated in their linear region. This novel MOSFET design has a promising application and has a better sensitivity compared to MOSFET exploiting a single effect or a similar piezoresistive or capacitive sensor.


10.1109/4.348 ◽  
1988 ◽  
Vol 23 (4) ◽  
pp. 972-977 ◽  
Author(s):  
J.T. Kung ◽  
H.-S. Lee ◽  
R.T. Howe

2013 ◽  
Vol 22 (04) ◽  
pp. 1350021
Author(s):  
XIAOMING CHEN ◽  
LING XIN ◽  
JIANWEI ZHANG ◽  
SONGSONG LI

Chemical-mechanical polishing (CMP) is an essential process in deep-submicrometer LSI manufacturing to achieve Chip's planarization. It includes two processes: back-end-of-line (BEOL) and front-end-of-line (FEOL). This paper focuses on the problem of BEOL in 65 nm copper process. Although model-based dummy metal fill has become a tendency recently, the proposed improved rule-based dummy fill is appropriate still. A middle scale design is used for simulation. The metal density, oxide thickness, copper thickness, capacitance variation and variation of layout data size were investigated. The results show that improved rule-based dummy fill and model-based dummy fill have the same planarization, and proposed method has small capacitance variation. The GDS file size of the proposed rule-based fill is less than the model-based fill's.


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