LC-VCO design optimization at 1/f 2 phase noise performance in 65 nm CMOS technology

2014 ◽  
Vol 80 (3) ◽  
pp. 499-506 ◽  
Author(s):  
Mingzhu Zhou ◽  
Lingling Sun ◽  
Liu Jun ◽  
Wang Jie
2011 ◽  
Vol 3 (6) ◽  
pp. 627-631 ◽  
Author(s):  
Paolo Lucchi ◽  
Davide Dermit ◽  
Gilles Jacquemod ◽  
Jean Baptiste Begueret ◽  
Mattia Borgarino

This paper reports a 15 GHz quadrature voltage controlled oscillator (QVCO) designed in a 130 nm CMOS technology. The phase noise performance of the QVCO and of a phase locked loop (PLL) where the QVCO was inserted were compared with the literature and with telecom standards and commercial products for broadcast satellite applications.


2012 ◽  
Vol 496 ◽  
pp. 527-533
Author(s):  
Na Bai ◽  
Hong Gang Zhou ◽  
Qiu Lei Wu ◽  
Chun Yu Peng

In this paper, ring oscillator phase noise caused by power supply noise (PSN) with deterministic frequency is analyzed. Results show that phase noise caused by deterministic noise is only an impulse series. Compared with the jitter caused by PSN, the phase noise caused by PSN with deterministic frequency contributes considerably less to total phase noise performance. To verify the analysis method, a CMOS ring oscillator is designed and fabricated using SMIC 0.13 µm CMOS process. Comparisons between the analytical results and measurements prove the accuracy of the proposed method


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