15 GHz quadrature voltage controlled oscillator in 130 nm CMOS technology

2011 ◽  
Vol 3 (6) ◽  
pp. 627-631 ◽  
Author(s):  
Paolo Lucchi ◽  
Davide Dermit ◽  
Gilles Jacquemod ◽  
Jean Baptiste Begueret ◽  
Mattia Borgarino
Keyword(s):  
Phase Noise ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Noise Performance ◽  
Commercial Products ◽  
Satellite Applications ◽  
Phase Noise Performance

This paper reports a 15 GHz quadrature voltage controlled oscillator (QVCO) designed in a 130 nm CMOS technology. The phase noise performance of the QVCO and of a phase locked loop (PLL) where the QVCO was inserted were compared with the literature and with telecom standards and commercial products for broadcast satellite applications.

A FULLY INTEGRATED MULTI-BAND LCVCO BASED ON CMOS TECHNOLOGY

2010 ◽  
Vol 19 (06) ◽  
pp. 1299-1305 ◽  
Author(s):  
XUEPO MA ◽  
WEI ZHANG ◽  
YANG LIU
Keyword(s):  
Phase Noise ◽  
Tuning Range ◽  
Low Frequency ◽  
Cmos Technology ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Worst Case ◽  
Fully Integrated ◽  
Phase Noise Performance ◽  
Multi Band

In this paper, a cross-coupled complementary inductance–capacitance voltage controlled oscillator (LCVCO) with low phase noise and wide tuning range is presented. It has a multi-band topology and was fabricated with RF CMOS technology. For the purpose of lowering the K VCO and reducing the nonlinearities of varactors, the sizes of the varactors are set small. Also noise filtering technique is adopted to minimize up-conversion of the low frequency noise as well as down-conversion of the high frequency noise, thus the phase noise performance of the VCO is greatly improved. Simulation and experimental results indicate that the LCVCO displays a phase noise of -126.1 dBc at 900 kHz offset in worst case with a tuning range from 1.76 to 1.96 GHz.

scholarly journals RF CMOS Oscillators Design for autonomous Connected Objects

2019 ◽  
Vol 88 ◽  
pp. 05001
Author(s):  
Fayrouz Haddad ◽  
Wenceslas Rahajandraibe ◽  
Imen Ghorbel
Keyword(s):  
Performance Optimization ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Noise Performance ◽  
Ultra Low Power ◽  
Wireless Transceiver ◽  
Cmos Oscillators ◽  
Phase Noise Performance

Voltage controlled oscillator (VCO) is an integral part of IoT wireless transceiver components. In this paper, VCOs operating around 2.4 GHz have been designed in CMOS technology. The relation between their components and specifications is studied for their performance optimization. Ultra-low power, less than 270 µW, has been obtained, while performing a frequency tuning range of about 10% between 2.1 and 2.4 GHz. Investigations on phase noise performance have been also achieved.

scholarly journals A 12 GHz 30 mW 130 nm CMOS Rotary Travelling Wave Voltage Controlled Oscillator

2012 ◽  
Vol 2012 ◽  
pp. 1-10
Author(s):  
G. Jacquemod ◽  
F. Ben Abdeljelil ◽  
L. Carpineto ◽  
W. Tatinian ◽  
M. Borgarino
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Cmos Technology ◽  
Travelling Wave ◽  
Voltage Controlled Oscillator ◽  
Satellite Applications

This paper reports a 12 GHz rotary travelling wave (RTW) voltage controlled oscillator designed in a 130 nm CMOS technology. The phase noise and power consumption performances were compared with the literature and with telecommunication standards for broadcast satellite applications. The RTW VCO exhibits a −106 dBc/Hz at 1 MHz and a 30 mW power consumption with a sensibility of 400 MHz/V. Finally, requirements are given for a PLL implementation of the RTW VCO and simulated results are presented.

Ring Oscillator Phase Noise Properties due to PSN with Deterministic Frequency

2012 ◽  
Vol 496 ◽  
pp. 527-533
Author(s):  
Na Bai ◽  
Hong Gang Zhou ◽  
Qiu Lei Wu ◽  
Chun Yu Peng
Keyword(s):  
Phase Noise ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Analysis Method ◽  
Noise Performance ◽  
Supply Noise ◽  
Total Phase ◽  
Phase Noise Performance ◽  
Oscillator Phase Noise ◽  
Oscillator Phase

In this paper, ring oscillator phase noise caused by power supply noise (PSN) with deterministic frequency is analyzed. Results show that phase noise caused by deterministic noise is only an impulse series. Compared with the jitter caused by PSN, the phase noise caused by PSN with deterministic frequency contributes considerably less to total phase noise performance. To verify the analysis method, a CMOS ring oscillator is designed and fabricated using SMIC 0.13 µm CMOS process. Comparisons between the analytical results and measurements prove the accuracy of the proposed method

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Sign in / Sign up

Export Citation Format

Share Document