Impact of multi threshold transistor in positive feedback source coupled logic (PFSCL) fundamental cell

This paper describes new sleep-based positive feedback source-coupled logic (PFSCL) tri-state inverter/buffer topologies. The tri-state behavior is obtained by disconnecting the circuit from both power supply and ground. This is achieved by placing additional transistors, driving the load transistor to cut off or disabling the current source. The combination of the three methods results in six new topologies. The functionality and performance of the proposed topologies is studied through SPICE simulations. A comparison with available sleep-based PFSCL tri-state buffer circuit shows a maximum reduction of 11% and 60% in the propagation delay and output enable time, respectively. The usefulness of the proposed topologies is illustrated through bus and D latch implementation.

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Modeling and Evaluation of Positive-Feedback Source-Coupled Logic

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2004.838149 ◽

2004 ◽

Vol 51 (12) ◽

pp. 2345-2355 ◽

Cited By ~ 29

Author(s):

M. Alioto ◽

L. Pancioni ◽

S. Rocchi ◽

V. Vignoli

Keyword(s):

Positive Feedback ◽

Feedback Source

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New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

Journal of Electrical and Computer Engineering ◽

10.1155/2011/670508 ◽

2011 ◽

Vol 2011 ◽

pp. 1-6 ◽

Cited By ~ 2

Author(s):

Kirti Gupta ◽

Ranjana Sridhar ◽

Jaya Chaudhary ◽

Neeta Pandey ◽

Maneesha Gupta

Keyword(s):

Low Power ◽

Positive Feedback ◽

Cmos Technology ◽

Performance Comparison ◽

Power Efficient ◽

Power Delay Product ◽

Feedback Source ◽

Design Techniques ◽

A Performance

Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.

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