An ultra-low power hybrid 2nd order feed forward ΔΣ modulator design for implantable medical devices

2021 ◽  
Author(s):  
Dalila Laouej ◽  
Houda Daoud ◽  
Mourad Loulou
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Implantable Medical Devices ◽  
Ultra Low Power ◽  
Feed Forward

Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices

2016 ◽  
pp. 199-228 ◽  
Author(s):  
Nabi Sertac Artan
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Sar Adc ◽  
The Other ◽  
Implantable Medical Devices ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
Electrophysiological Signals ◽  
Recent Developments ◽  
Adc Architectures

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.

scholarly journals An Ultra-Low Power Implantable Medical Devices: An Engineering Perspective

2021 ◽  
Vol 23 (12) ◽  
pp. 46-59
Author(s):  
B. Sathyabhama ◽  
◽  
B. Siva Shankari ◽  
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Neurological Disorders ◽  
Heart Diseases ◽  
Implantable Devices ◽  
Implantable Medical Device ◽  
Implantable Medical Devices ◽  
Ultra Low Power ◽  
Device Integration ◽  
History Of

Implantable Medical Devices (IMDs) reside within human bodies either temporarily or permanently, for diagnostic, monitoring, or therapeutic purposes. IMDs have a history of outstanding success in the treatment of many diseases, including heart diseases, neurological disorders, and deafness etc.,With the ever-increasing clinical need for implantable devices comes along with the continuous flow of technical challenges. Comparing with the commercial portable products, implantable devices share the same need to reduce size, weight and power. Thus, the need for device integration becomes very much imperative. There are many challenges faced when creating an implantable medical device. While this paper focuses on various techniques adapted to design a reliable device and also focus on the key electronic features of designing an ultra-low power implantable medical circuits for devices and systems.

Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices

2018 ◽  
pp. 413-443
Author(s):  
Nabi Sertac Artan
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Sar Adc ◽  
The Other ◽  
Implantable Medical Devices ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
Electrophysiological Signals ◽  
Recent Developments ◽  
Adc Architectures

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.

Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices

2018 ◽  
pp. 231-261
Author(s):  
Nabi Sertac Artan
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Sar Adc ◽  
The Other ◽  
Implantable Medical Devices ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
Electrophysiological Signals ◽  
Recent Developments ◽  
Adc Architectures

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.

An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications

2019 ◽  
Vol 29 (04) ◽  
pp. 2050056
Author(s):  
Sahel Javahernia ◽  
Esmaeil Najafi Aghdam ◽  
Pooya Torkzadeh
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Digital To Analog Converter ◽  
Ultra Low Power ◽  
Feed Forward ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Summing Amplifier ◽  
Capacitor Structure ◽  
Asynchronous Sar

In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [Formula: see text] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[Formula: see text][Formula: see text]m CMOS technology achieves 95.98[Formula: see text]dB peak signal-to-noise and distortion (SNDR) for 10[Formula: see text]KHz signal bandwidth and dissipates 44[Formula: see text][Formula: see text]w while its FOM is obtained about 43 fJ/conv.-step.

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