Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices

2018 ◽  
pp. 413-443
Author(s):  
Nabi Sertac Artan

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.

Author(s):  
Nabi Sertac Artan

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.


2018 ◽  
pp. 231-261
Author(s):  
Nabi Sertac Artan

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.


2021 ◽  
Vol 23 (12) ◽  
pp. 46-59
Author(s):  
B. Sathyabhama ◽  
◽  
B. Siva Shankari ◽  

Implantable Medical Devices (IMDs) reside within human bodies either temporarily or permanently, for diagnostic, monitoring, or therapeutic purposes. IMDs have a history of outstanding success in the treatment of many diseases, including heart diseases, neurological disorders, and deafness etc.,With the ever-increasing clinical need for implantable devices comes along with the continuous flow of technical challenges. Comparing with the commercial portable products, implantable devices share the same need to reduce size, weight and power. Thus, the need for device integration becomes very much imperative. There are many challenges faced when creating an implantable medical device. While this paper focuses on various techniques adapted to design a reliable device and also focus on the key electronic features of designing an ultra-low power implantable medical circuits for devices and systems.


2018 ◽  
Vol 7 (2.12) ◽  
pp. 257
Author(s):  
K A. Jyotsna ◽  
P Satish Kumar ◽  
B K. Madhavi ◽  
I Swaroopa

The trends of the VLSI technology is advancing, due to this majority of the industry players are showing interest in development of the devices with ultra low power applications. Analog-to-Digital converters are getting extensively used in Medical implant machines and in lots of Sensor machines, because it is serving an imperative role in interfacing between analog signal and digital signal. This paper presents a modernistic technique called as Sub threshold Current Mode Logic (CML) for ultra low power digital components. Here 16 bit SAR ADC is designed and compared with the techniques like CMOS and STCML for power consumption and delay. Schematics are materialized with Cadence Virtuoso tool using 45nm process. The transistors in these CML and CMOS operate at threshold voltages and Sub-threshold voltages where the executable design is done using 1V to 0.5V power supply (VDD). The comparator dissipates aggrandized power, so most of the intension is converged on forming this chunk. The CML logic procedure operates primarily with the current domain, due to this the performance can be constitutionally high. This approach decreases static power dissipation.


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