Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools

Journal of Electronic Testing ◽

10.1007/s10836-014-5490-4 ◽

2014 ◽

Vol 30 (6) ◽

pp. 763-780 ◽

Author(s):

Yu Zhang ◽

Bei Zhang ◽

Vishwani D. Agrawal

Keyword(s):

Fault Detection ◽

Diagnostic Test ◽

Test Generation ◽

Delay Faults ◽

Transition Delay

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Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation

Journal of Electronic Testing ◽

10.1007/s10836-010-5142-2 ◽

2010 ◽

Vol 26 (2) ◽

pp. 165-176 ◽

Author(s):

Maheshwar Chandrasekar ◽

Nikhil P. Rahagude ◽

Michael S. Hsiao

Keyword(s):

Diagnostic Test ◽

Test Generation ◽

Incremental Learning ◽

Learning Framework

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Diagnostic Test Generation for Arbitrary Faults

2006 IEEE International Test Conference ◽

10.1109/test.2006.297647 ◽

2006 ◽

Author(s):

Naresh Bhatti ◽

R.D. Blanton

Keyword(s):

Diagnostic Test ◽

Test Generation

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An Automatic Test Generation Method for Crosstalk Delay Faults Using Modified FAN Algorithm

Test Generation of Crosstalk Delay Faults in VLSI Circuits ◽

10.1007/978-981-13-2493-2_4 ◽

2018 ◽

pp. 57-77

Author(s):

S. Jayanthy ◽

M. C. Bhuvaneswari

Keyword(s):

Test Generation ◽

Delay Faults ◽

Automatic Test Generation ◽

Automatic Test ◽

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Distinguishing dynamic bridging faults and transition delay faults

2015 IEEE 11th International Conference on ASIC (ASICON) ◽

10.1109/asicon.2015.7516978 ◽

2015 ◽

Author(s):

Cheng-Hung Wu ◽

Saint James Lee ◽

Kuen-Jong Lee

Keyword(s):

Delay Faults ◽

Bridging Faults ◽

Transition Delay

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Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

IEICE Transactions on Information and Systems ◽

10.1587/transinf.e96.d.1323 ◽

2013 ◽

Vol E96.D (6) ◽

pp. 1323-1331

Author(s):

Yoshinobu HIGAMI ◽

Hiroshi TAKAHASHI ◽

Shin-ya KOBAYASHI ◽

Kewal K. SALUJA

Keyword(s):

Test Generation ◽

Delay Faults ◽

Test Environment

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.476581 ◽

1995 ◽

Vol 14 (12) ◽

pp. 1505-1515 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy ◽

P. Uppaluri

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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Deterministic broadside test generation for transition path delay faults

Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10 ◽

10.1145/1785481.1785514 ◽

2010 ◽

Author(s):

Bo Yao ◽

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay Faults ◽

Transition Path

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SIMULATION BASED LOW POWER TEST GENERATION FOR CROSSTALK DELAY FAULTS

International Journal of Modelling and Simulation ◽

10.2316/journal.205.2011.3.205-5524 ◽

2011 ◽

Vol 31 (3) ◽

Author(s):

Jayanthy Soundararajan ◽

Bhuvaneswari M. Chinnadurai

Keyword(s):

Low Power ◽

Test Generation ◽

Delay Faults ◽

Low Power Test ◽

Simulation Based

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Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors

2020 23rd Euromicro Conference on Digital System Design (DSD) ◽

10.1109/dsd51259.2020.00105 ◽

2020 ◽

Author(s):

Adeboye Stephen Oyeniran ◽

Raimund Ubar ◽

Maksim Jenihhin ◽

Jaan Raik

Keyword(s):

Functional Test ◽

Delay Faults ◽

Transition Delay

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Short single tests for circuits with arbitrary stuck-at faults at outputs of gates

Discrete Mathematics and Applications ◽

10.1515/dma-2019-0030 ◽

2019 ◽

Vol 29 (5) ◽

pp. 321-333

Author(s):

Kirill A. Popkov

Keyword(s):

Fault Detection ◽

Boolean Function ◽

Diagnostic Test ◽

List Type ◽

Abstract The following results are proved: any nonconstant Boolean function may be implemented by an irredundant circuit of gates in the basis {x& y, x, x ⊕ y ⊕ z} admitting a single fault detection test of length at most 2 with respect to arbitrary stuck-at faults at outputs of gates, there exists a six-place Boolean function ψ such that any nonconstant Boolean function may be implemented by an irredundant circuit of gates in the basis {ψ} admitting a single diagnostic test of length at most 3 with respect to arbitrary stuck-at faults at outputs of gates.

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