Test Flow Selection for Stacked Integrated Circuits

Journal of Electronic Testing ◽

10.1007/s10836-019-05813-z ◽

2019 ◽

Vol 35 (4) ◽

pp. 425-440

Author(s):

Breeta SenGupta ◽

Dimitar Nikolov ◽

Assmitra Dash ◽

Erik Larsson

Keyword(s):

Integrated Circuits ◽

Test Flow ◽

Selection For ◽

Stacked Integrated Circuits

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Benefits of vertically stacked integrated circuits for sequential logic

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96 ◽

10.1109/iscas.1996.541915 ◽

2002 ◽

Author(s):

M. Reber ◽

R. Tielert

Keyword(s):

Integrated Circuits ◽

Sequential Logic ◽

Stacked Integrated Circuits

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MCDM Applied to the Partitioning Problem of 3D-Stacked Integrated Circuits

Multiple Criteria Decision Making ◽

10.1007/978-3-319-39292-9_9 ◽

2016 ◽

pp. 165-187 ◽

Author(s):

Nguyen Anh Vu Doan ◽

Dragomir Milojevic ◽

Yves De Smet

Keyword(s):

Integrated Circuits ◽

Partitioning Problem ◽

Stacked Integrated Circuits

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Thermal Simulation of 3-D Stacked Integrated Circuits with Layered Finite Element Method

2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall) ◽

10.1109/piers-fall48861.2019.9021638 ◽

2019 ◽

Author(s):

Bo Li ◽

Min Tang ◽

Yuwen Zhi ◽

Huixian Yu

Keyword(s):

Finite Element Method ◽

Finite Element ◽

Integrated Circuits ◽

Thermal Simulation ◽

Element Method ◽

Stacked Integrated Circuits

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Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

2009 IEEE International Conference on 3D System Integration ◽

10.1109/3dic.2009.5306587 ◽

2009 ◽

Author(s):

Dragomir Milojevic ◽

Trevor E. Carlson ◽

Kris Croes ◽

Riko Radojcic ◽

Diana F. Ragett ◽

...

Keyword(s):

Integrated Circuits ◽

Practical Case ◽

Stacked Integrated Circuits

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Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits

Journal of Electronic Testing ◽

10.1007/s10836-012-5279-2 ◽

2012 ◽

Vol 28 (1) ◽

pp. 13-14 ◽

Author(s):

Erik Jan Marinissen ◽

Yervant Zorian

Keyword(s):

Integrated Circuits ◽

Guest Editorial ◽

Special Issue ◽

Editorial Special Issue ◽

Stacked Integrated Circuits

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Test-cost optimization and test-flow selection for 3D-stacked ICs

2013 IEEE 31st VLSI Test Symposium (VTS) ◽

10.1109/vts.2013.6548941 ◽

2013 ◽

Author(s):

M. Agrawal ◽

K. Chakrabarty

Keyword(s):

Cost Optimization ◽

Test Cost ◽

Test Flow ◽

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An effective and efficient numerical method for thermal management in 3D stacked integrated circuits

Applied Thermal Engineering ◽

10.1016/j.applthermaleng.2017.04.080 ◽

2017 ◽

Vol 121 ◽

pp. 200-209 ◽

Author(s):

Chengdi Xiao ◽

Hu He ◽

Junhui Li ◽

Sen Cao ◽

Wenhui Zhu

Keyword(s):

Integrated Circuits ◽

Numerical Method ◽

Thermal Management ◽

Stacked Integrated Circuits

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Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits

2009 International Symposium on System-on-Chip ◽

10.1109/socc.2009.5335663 ◽

2009 ◽

Author(s):

Dragomir Milojevic ◽

Riko Radojcic ◽

Roger Carpenter ◽

Pol Marchal

Keyword(s):

Integrated Circuits ◽

Design Methodology ◽

Stacked Integrated Circuits

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Time-multiplexed test access architecture for stacked integrated circuits

IEICE Electronics Express ◽

10.1587/elex.13.20160314 ◽

2016 ◽

Vol 13 (14) ◽

pp. 20160314-20160314

Author(s):

Muhammad Adil Ansari ◽

Jihun Jung ◽

Dooyoung Kim ◽

Sungju Park

Keyword(s):

Integrated Circuits ◽

Stacked Integrated Circuits

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On the use of Multi-Criteria Decision Aid tools for the efficient design of 3D-Stacked Integrated Circuits: A preliminary study

2010 IEEE International Conference on Industrial Engineering and Engineering Management ◽

10.1109/ieem.2010.5674222 ◽

2010 ◽

Author(s):

N. A. V. Doan ◽

Y. De Smet ◽

F. Robert ◽

D. Milojevic

Keyword(s):

Integrated Circuits ◽

Decision Aid ◽

Efficient Design ◽

Preliminary Study ◽

Stacked Integrated Circuits

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