scholarly journals An Efficient FIR Filter Based on Hardware Sharing Architecture Using CSD Coefficient Grouping for Wireless Application

2021 ◽  
Author(s):  
Ajeet Kumar Srivastava ◽  
Krishna Raj
Keyword(s):  
Fir Filter ◽  
Wireless Application ◽  
Hardware Sharing

scholarly journals An efficient FIR filter based on hardware sharing  architecture using CSD coefficient grouping for wireless application

2021 ◽  
Author(s):  
AJEET KUMAR SRIVAST ◽  
Krishna Raj
Keyword(s):  
Average Power ◽  
Processing System ◽  
Number System ◽  
Fir Filter ◽  
Filter Coefficient ◽  
Operation Speed ◽  
Average Power Consumption ◽  
Wireless Application ◽  
Grouping Method ◽  
Hardware Sharing

Abstract FIR filter is an essential part of digital signal processing that is extensively used in many areas such as wireless application and digital processing system. An efficient recursive filter is always required for real-time applications such as 5G network, smart robots and Internet of Things etc. The design of FIR filter is inherently stable and has a linear phase characteristic but its implementation often involves complexity and a large filter length to achieve specific design requirements. In this paper, the complexity of FIR filter is reduced by eliminating the repeated subexpression in a canonic sign digit(CSD)number system based filter operation. A new grouping method has been proposed for the CSD number system-based filter coefficient to minimize the number of unpaired nonzero bits in the filter coefficient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11% as compared to other existing schemes. Further, an efficient FIR filter with hardware sharing architecture is designed and implemented to achieve a 14.65% reduction in average power consumption and the average operation speed is increased by 10.1% in comparison to the other existing filter structures.

A Single Band Antenna Design for Future Millimeter Wave Wireless Communication at 38 GHz

2018 ◽  
Vol 3 (1) ◽  
pp. 35 ◽  
Author(s):  
Cihat Şeker ◽  
Turgut Ozturk ◽  
Muhammet Tahir Güneşer
Keyword(s):  
Millimeter Wave ◽  
Mobile Communications ◽  
Return Loss ◽  
Computer Software ◽  
Dielectric Substrate ◽  
Single Band ◽  
Microstrip Patch ◽  
Fifth Generation ◽  
Wireless Application ◽  
5G Mobile Communications

In this proposed paper, a single band microstrip patch antenna for fifth generation (5G) wireless application was presented. 28, 38, 60 and 73 GHz frequency bands have been allocated for 5G mobile communications by International Telecommunications Union (ITU). In this paper, we proposed an antenna, which is suitable for the millimeter wave frequency. The single band antenna consists of new slot loaded on the radiating patch with the 50 ohms microstrip line feeding used. This single band antenna was simulated on a FR4 dielectric substrate have relative permittivity 4.4, loss tangent 0.02, and height 1.6 mm. The antenna was simulated by Electromagnetic simulation, computer software technology High Frequency Structural Simulator. And simulated result on return loss, VSWR, radiation pattern and 3D gain was presented. The parameters of the results well coherent and proved the literature for millimeter wave 5G wireless application at 38 GHz.

Design of FIR Filter for Efficient FPGA Implementation

2015 ◽  
Vol 5 (3) ◽  
pp. 1-10
Author(s):  
S. V. Padmajarani ◽  
◽  
M. Muralidhar ◽  
Keyword(s):  
Fir Filter ◽  
Fpga Implementation

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

Sign in / Sign up

Export Citation Format

Share Document