An efficient FIR filter based on hardware sharing architecture using CSD coefficient grouping for wireless application

FIR filter is an essential part of digital signal processing that is extensively used in many areas such as wireless application and digital processing system. An efficient recursive filter is always required for real-time applications such as 5G network, smart robots and Internet of Things etc. The design of FIR filter is inherently stable and has a linear phase characteristic but its implementation often involves complexity and a large filter length to achieve specific design requirements. In this paper, the complexity of FIR filter is reduced by eliminating the repeated subexpression in a canonic sign digit(CSD)number system based filter operation. A new grouping method has been proposed for the CSD number system-based filter coefficient to minimize the number of unpaired nonzero bits in the filter coefficient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11% as compared to other existing schemes. Further, an efficient FIR filter with hardware sharing architecture is designed and implemented to achieve a 14.65% reduction in average power consumption and the average operation speed is increased by 10.1% in comparison to the other existing filter structures.

Hardware Sharing for Channel Interleavers in 5G NR Standard

Interleaver module is an important part of modern mobile communication system. It plays an important role in reducing bit error rate and improving transmission efficiency over fading channels. In 5G NR (5th Generation New Radio) standards, LDPC (low-density parity-check) and polar channel codes are employed for data channels and control channels, respectively. If multiple interleavers are implemented separately for them, the cost increases significantly. To address this issue, a hardware multiplexing scheme for channel interleavers based on LDPC and polar codes is proposed in this paper. Firstly, the formulas for the processes of the control channel interleaving and data channel interleaving are derived with respect to 5G NR standard. Then, the hardware implementation structures of the two interleavers are given. Subsequently, hardware reuse is proposed by sharing the similar or identical parts between the two hardware structures. Simulation results verify the correctness of our proposed scheme and demonstrate that it can realize the hardware sharing of the two kinds of channel interleavers to reduce the cost of silicon.

HARDWARE-EFFICIENT MULTI-STANDARD VIDEO TRANSFORM CORE

This study presents a unified hybrid architecture to compute the inverse discrete cosine transform (IDCT) of multiple modern video decoders such as moving picture experts group (MPEG-4), H.264, VC-1 and high efficiency video coding (HEVC). The proposed hardware sharing architecture requires a lower hardware cost than that for individual implementations, and maximizes the proportion of the circuit that is reused during the computation. The proposed architecture design needs only adders and shifters to significantly reduce the hardware cost. Thus, the resource sharing method can increase the circuit sharing capability and achieve high hardware efficiency. For verification, a TSMC 0.18-μm CMOS process is applied to implement the IDCT chip, and the maximum throughput rate of the proposed design is 1000 MP/s with a hardware cost of 16.5 k gates.