A “ballistic” analog memory device for neural network implementation

1991 ◽  
Vol 34 (8) ◽  
pp. 919-920
Author(s):  
Takashi Morie
1993 ◽  
Vol 40 (11) ◽  
pp. 2029-2035 ◽  
Author(s):  
O. Fujita ◽  
Y. Amemiya

Author(s):  
T. Patrick Xiao ◽  
Ben Feinberg ◽  
Christopher H. Bennett ◽  
Vineet Agrawal ◽  
Prashant Saxena ◽  
...  

1992 ◽  
Vol 258 ◽  
Author(s):  
A A Reeder ◽  
I P Thomas ◽  
C Smith ◽  
J Wittgreffe ◽  
D J Godfrey ◽  
...  

ABSTRACTThe amorphous silicon memory device shows promise as an analogue weight element in neural networks. The device resistance can be programmed to within 5% of any specific value between lkΩ and lMΩ using 10ns to 1μ voltage pulses in the range 1–5V. In this paper we describe the physical structure of the element and its electrical characteristics. Finally, a simple example is discussed of a small neural network implementing the EXOR function using amorphous silicon memory elements as a resistive array of weights and external op-amps as the current summing nodes.


2018 ◽  
Vol 75 ◽  
pp. 147-152 ◽  
Author(s):  
Qin Li ◽  
Yuntao Wu ◽  
Huifeng Zhu ◽  
Qi Wei ◽  
Fei Qiao ◽  
...  

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