A novel two-fold state skip logic Built-In Self-Test scheme for digital circuits

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2015.04.013 ◽

2015 ◽

Vol 48 ◽

pp. 239-246

Author(s):

Anbalagan Kavitha ◽

Subramanian SasiKumar

Keyword(s):

Digital Circuits ◽

Test Scheme ◽

Self Test ◽

Built In Self Test

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A transparent built-in self-test scheme for detecting single V-coupling faults in RAMs

Proceedings of IEEE International Workshop on Memory Technology, Design, and Test ◽

10.1109/mtdt.1994.397187 ◽

2002 ◽

Author(s):

B.F. Cockburn ◽

Y.-F.N. Sat

Keyword(s):

Test Scheme ◽

Coupling Faults ◽

Self Test ◽

Built In Self Test

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Design and Testing of Combinational Logic Circuits Using Built in Self Test Scheme for FPGAs

2015 Fifth International Conference on Communication Systems and Network Technologies ◽

10.1109/csnt.2015.151 ◽

2015 ◽

Author(s):

Nagaraj S. Vannal ◽

Saroja V. Siddamal ◽

Shruthi V. Bidaralli ◽

Mahalaxmi S. Bhille

Keyword(s):

Logic Circuits ◽

Test Scheme ◽

Combinational Logic ◽

Combinational Logic Circuits ◽

Self Test ◽

Built In Self Test ◽

Design And Testing

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VDDQ: a built-in self-test scheme for analog on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard

Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) ◽

10.1109/iccdcs.2002.1004083 ◽

2003 ◽

Author(s):

G.O.D. Acevedo ◽

J. Ramirez-Angulo

Keyword(s):

Test Scheme ◽

Mixed Signal ◽

Self Test ◽

Built In Self Test ◽

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A programmable online/off-line built-in self-test scheme for RAMs with ECC

2009 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2009.5118183 ◽

2009 ◽

Author(s):

Hsing-Chen Lu ◽

Jin-Fu Li

Keyword(s):

Test Scheme ◽

Self Test ◽

Built In Self Test

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A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs

Journal of Electronic Testing ◽

10.1007/s10677-004-4250-4 ◽

2004 ◽

Vol 20 (6) ◽

pp. 623-638 ◽

Author(s):

Sunil Rafeeque K.P. ◽

Vinita Vasudevan

Keyword(s):

Test Scheme ◽

Self Test ◽

Built In Self Test ◽

Binary Weighted

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A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals

IEICE Transactions on Electronics ◽

10.1093/ietele/e91-c.10.1713 ◽

2008 ◽

Vol E91-C (10) ◽

pp. 1713-1716 ◽

Author(s):

Y. KIM ◽

K. KIM ◽

I. KIM ◽

S. KANG

Keyword(s):

Phase Locked Loops ◽

Test Scheme ◽

Digital Signals ◽

Self Test ◽

Built In Self Test

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A built in self test scheme for automatic interconnect fault diagnosis in multiple and single FPGA systems

2007 50th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2007.4488577 ◽

2007 ◽

Author(s):

M. Y. Niamat ◽

Arunjit Sahni ◽

M. M. Jamali

Keyword(s):

Fault Diagnosis ◽

Test Scheme ◽

Self Test ◽

Built In Self Test

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A Built-In Self-Test (BIST) Technique for Single-Event Testing in Digital Circuits

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2008.2006499 ◽

2008 ◽

Vol 55 (6) ◽

pp. 3130-3135 ◽

Author(s):

Anitha Balasubramanian ◽

B. L. Bhuva ◽

L. W. Massengill ◽

B. Narasimham ◽

R. L. Shuler ◽

...

Keyword(s):

Digital Circuits ◽

Single Event ◽

Self Test ◽

Built In Self Test

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A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

29th VLSI Test Symposium ◽

10.1109/vts.2011.5783749 ◽

2011 ◽

Author(s):

Yu-Jen Huang ◽

Jin-Fu Li ◽

Ji-Jan Chen ◽

Ding-Ming Kwai ◽

Yung-Fa Chou ◽

...

Keyword(s):

Test Scheme ◽

3D Ics ◽

Self Test ◽

Built In Self Test

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A Built-In Self-Test Scheme for Soft Error Rate Characterization

2008 14th IEEE International On-Line Testing Symposium ◽

10.1109/iolts.2008.26 ◽

2008 ◽

Author(s):

Alodeep Sanyal ◽

Syed M. Alam ◽

Sandip Kundu

Keyword(s):

Test Scheme ◽

Soft Error Rate ◽

Self Test ◽

Built In Self Test

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