Thermal mismatch induced disorder of beta-eucryptite and its effect on thermal expansion of beta-eucryptite/Al composites

2012 ◽  
Vol 72 (13) ◽  
pp. 1613-1617 ◽  
Author(s):  
L.D. Wang ◽  
Z.W. Xue ◽  
Y. Cui ◽  
K.P. Wang ◽  
Y.J. Qiao ◽  
...  
Author(s):  
Abderrazzak El Boukili

Purpose – The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials and manufacturers as Intel or IBM to boost the performances of the nanoscale PMOS and NMOS transistors. It is now admitted that compressive stress enhances the mobility of holes and tensile stress enhances the mobility of electrons in the channel. Design/methodology/approach – During thermal processing, thin film materials like polysilicon, silicon nitride, silicon dioxide, or SiGe expand or contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The author defines the thermal expansion coefficient as the rate of change of strain with respect to temperature. Findings – Several numerical experiments have been used for different temperatures ranging from 30 to 1,000°C. These experiments did show that the temperature affects strongly the extrinsic stress in the channel of a 45 nm PMOS transistor. On the other hand, the author has compared the extrinsic stress due to lattice mismatch with the extrinsic stress due to thermal mismatch. The author found that these two types of stress have the same order (see the numerical results on Figures 4 and 12). And, these are great findings for semiconductor industry. Practical implications – Front-end process induced extrinsic stress is used by manufacturers of nanoscale transistors as the new scaling vector for the 90 nm node technology and below. The extrinsic stress has the advantage of improving the performances of PMOSFETs and NMOSFETs transistors by enhancing mobility. This mobility enhancement fundamentally results from alteration of electronic band structure of silicon due to extrinsic stress. Then, the results are of great importance to manufacturers and industrials. The evidence is that these results show that the extrinsic stress in the channel depends also on the thermal mismatch between materials and not only on the material mismatch. Originality/value – The model the author is proposing to calculate the initial stress due to thermal mismatch is novel and original. The author validated the values of the initial stress with those obtained by experiments in Al-Bayati et al. (2005). Using the uniaxial stress generation technique of Intel (see Figure 2). Al-Bayati et al. (2005) found experimentally that for 17 percent germanium concentration, a compressive initial stress of 1.4 GPa is generated inside the SiGe layer.


2017 ◽  
Vol 19 (19) ◽  
pp. 11778-11785 ◽  
Author(s):  
Chang Zhou ◽  
Qiang Zhang ◽  
Saiyue Liu ◽  
Bingcheng Luo ◽  
Eongyu Yi ◽  
...  

Fully dense Y2Mo3O12/Al composites were prepared by squeeze casting.


2018 ◽  
Vol 6 (42) ◽  
pp. 11407-11415 ◽  
Author(s):  
Pawan Kumar ◽  
Birender Singh ◽  
Pradeep Kumar ◽  
Viswanath Balakrishnan

Formation of heterophase WS2 cancels the competing thermal mismatch and lattice strains and stabilizes crack free monolayer heterostructures while homophase monolayer suffers from severe cracking.


2018 ◽  
Vol 202 ◽  
pp. 01005
Author(s):  
D. Sujan ◽  
L. Vincent ◽  
Y. W. Pok

In electronic packaging, typically two or more thin dissimilar plates or layers are bonded together by an extremely thin adhesive bond layer. Electronic assemblies are usually operated under high power conditions which predictably produces a high temperature environment in the electronic devices. Therefore, thermal mismatch shear and peeling stress inevitably arise at the interfaces of the bonded dissimilar materials due to differences in Coefficient of Thermal Expansion (CTE) typically during the high temperature change in the bond process. As a result, delamination failure may occur during manufacturing, machining, and field use. As such, these thermo-mechanical stresses play a very significant role in the design and reliability of the electronic packaging assembly. Consequently, critical investigations of interfacial stresses under variable load conditions in composite structure can result in a better design of electronic packaging with higher reliability and minimize or eliminate the risk of functional failure. In order to formulize bond material selection, analytical studies are carried out in order to study the influence of bond layer parameters on interfacial thermal stresses of a given package. These parameters include Coefficient of thermal expansion (CTE), poison’s ratio, temperature, thickness, and stiffness (compliant and stiff) of the bond layer. From the study, stiffness and bond layer thickness are identified as the key parameters influencing interfacial shearing and peeling stresses. The other parameters namely CTE, poisons ratio has shown insignificant influence on interfacial stresses due to the very thin section of bond layer compared to the top and bottom layers. The results also show that the interfacial stresses increases proportionally with the increase of temperature in the layers. Therefore, it is very important that the temperature is maintained as low as possible during the chip manufacturing and operating stages. Since only two parameters namely stiffness and bond layer thickness are identified as the key parameters, the interface thermal mismatch stresses can be reduced or eliminated by controlling these two parameters only. Therefore the identification of suitable bond layer parameters selection with reasonable accuracy is possible even without performing optimization process. Finally, this paper proposes a Metal Matrix Composite (MMC) bond material selection approach using rule of mixture material design. The outcome of this research can be seen in the forms of practical and beneficial tools for interfacial stress evaluation and physical design and fabrication of layered assemblies. The Engineers can utilize this research outcome in conjunction with guidelines for electronic packaging under variable thermal properties of layered composites.


Author(s):  
J. Cooper ◽  
O. Popoola ◽  
W. M. Kriven

Nickel sulfide inclusions have been implicated in the spontaneous fracture of large windows of tempered plate glass. Two alternative explanations for the fracture-initiating behaviour of these inclusions have been proposed: (1) the volume increase which accompanies the α to β phase transformation in stoichiometric NiS, and (2) the thermal expansion mismatch between the nickel sulfide phases and the glass matrix. The microstructure and microchemistry of the small inclusions (80 to 250 μm spheres), needed to determine the cause of fracture, have not been well characterized hitherto. The aim of this communication is to report a detailed TEM and EDS study of the inclusions.


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