The influence of operation temperature on the output properties of amorphous silicon-related solar cells

2005 ◽  
Vol 85 (2) ◽  
pp. 167-175 ◽  
Author(s):  
Masaki Shima ◽  
Masao Isomura ◽  
Ken-ichiro Wakisaka ◽  
Kenji Murata ◽  
Makoto Tanaka
2020 ◽  
Vol 1 (1) ◽  
pp. 31-37
Author(s):  
Ahnaf Shahriar ◽  
◽  
Saif Hasnath ◽  
Md. Aminul Islam

Solar photovoltaic technology is one of the most promising, economical and green technologies to harvest energy with the least effect on the environment. Crystalline silicon (c-Si), amorphous silicon (a-Si), CIGS, CdTe/CdS etc., are dominating the PV market. Operating temperature plays an important role in the performance of solar cells. A comparative investigation on the effect of operating temperature on the market available solar cells is very important in choosing the better PV technology in high-temperature applications. In this study, the performances of different solar cell technologies, namely crystalline silicon (c-Si), amorphous silicon (a-Si), CIGS, and CdTe/CdS based solar cells, have been investigated under different operating temperature by using SCAPS-1D simulation software. All parameter of a solar cell for different technology has been studied under the varying operation temperature ranging from 25 ºC to 70 ºC and the rate of change of them has been recorded. It has been found that the Voc and Pmax degrade significantly and Isc increases slightly with an increase in temperature. The temperature coefficients of Pmax for c-Si, a-Si, CdTe and CIGS have been found as -0.0724/K, -0.0362/K, -0.0112/K and -0.0663/K, respectively. On the other hand, c-Si and CIGS technologies show better quantum efficiency behaviour in both room and high operating temperatures.


Solar Cells ◽  
1986 ◽  
Vol 17 (2-3) ◽  
pp. 191-200 ◽  
Author(s):  
Tokumi Mase ◽  
Hiroshi Takei ◽  
Makoto Konagai ◽  
Kiyoshi Takahashi

2021 ◽  
Vol 108 ◽  
pp. 104960
Author(s):  
Issa Etier ◽  
Anas Al Tarabsheh ◽  
Nithiyananthan Kannan

Solar Energy ◽  
2013 ◽  
Vol 97 ◽  
pp. 591-595 ◽  
Author(s):  
C. Banerjee ◽  
T. Srikanth ◽  
U. Basavaraju ◽  
R.M. Tomy ◽  
M.G. Sreenivasan ◽  
...  

2006 ◽  
Vol 910 ◽  
Author(s):  
Qi Wang ◽  
Matt P. Page ◽  
Eugene Iwancizko ◽  
Yueqin Xu ◽  
Yanfa Yan ◽  
...  

AbstractWe have achieved an independently-confirmed 17.8% conversion efficiency in a 1-cm2, p-type, float-zone silicon (FZ-Si) based heterojunction solar cell. Both the front emitter and back contact are hydrogenated amorphous silicon (a-Si:H) deposited by hot-wire chemical vapor deposition (HWCVD). This is the highest reported efficiency for a HWCVD silicon heterojunction (SHJ) solar cell. Two main improvements lead to our most recent increases in efficiency: 1) the use of textured Si wafers, and 2) the application of a-Si:H heterojunctions on both sides of the cell. Despite the use of textured c-Si to increase the short-circuit current, we were able to maintain the same 0.65 V open-circuit voltage as on flat c-Si. This is achieved by coating a-Si:H conformally on the c-Si surfaces, including covering the tips of the anisotropically-etched pyramids. A brief atomic H treatment before emitter deposition is not necessary on the textured wafers, though it was helpful in the flat wafers. It is essential to high efficiency SHJ solar cells that the emitter grows abruptly as amorphous silicon, instead of as microcrystalline or epitaxial Si. The contact on each side of the cell comprises a thin (< 5 nm) low substrate temperature (~100°C) intrinsic a-Si:H layer, followed by a doped layer. Our intrinsic layers are deposited at 0.3-1.2 nm/s. The doped emitter and back-contact layers were deposited at a higher temperature (>200°C) and grown from PH3/SiH4/H2 and B2H6/SiH4/H2 doping gas mixtures, respectively. This combination of low (intrinsic) and high (doped layer) growth temperatures was optimized by lifetime and surface recombination velocity measurements. Our rapid efficiency advance suggests that HWCVD may have advantages over plasma-enhanced (PE) CVD in fabrication of high-efficiency heterojunction c-Si cells; there is no need for process optimization to avoid plasma damage to the delicate, high-quality, Si wafers.


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