VLSI Implementation of Balanced Binary Tree Decomposition Based 2048-Point FFT/IFFT Processor for Mobile WI-Max

2010 ◽  
Author(s):  
A D Darji ◽  
M S Patil
Keyword(s):  
Binary Tree ◽  
Vlsi Implementation ◽  
Tree Decomposition

scholarly journals A VLSI Design for Implementation of Transform Domain Adaptive Filters

VLSI Design ◽  
1999 ◽  
Vol 9 (2) ◽  
pp. 119-133
Author(s):  
Ali Najafi ◽  
Behrouz Farhang-Boroujeny ◽  
Ganesh S. Samudra
Keyword(s):  
Digital Signal Processor ◽  
Binary Tree ◽  
Adaptive Filters ◽  
Vlsi Design ◽  
Digital Signal ◽  
Vlsi Implementation ◽  
Transform Domain ◽  
Memory Scheme ◽  
Read Only Memory ◽  
On Chip

A VLSI implementation of a dedicated digital signal processor is presented. The processor is tailored for efficient implementation of transform domain adaptive filters. It incorporates a butterfly processor which performs butterfly operation to implement the required transformation. It is also able to perform complex addition, subtraction and multiplication. The butterfly processor makes use of a redundant binary tree multiplier with a recently proposed coding of signed-digit numbers which reduces the number of levels in the tree by one. An on-chip read only memory holds the transformation coefficients. The contents of the ROM determine the type of transform. The processor incorporates an ALU to perform integer arithmetic, address calculations and implementation of circular memory scheme. For fastest accessibility, the essential variables of the algorithm are implemented in a register fire.

scholarly journals Lossless image coding using binary tree decomposition of prediction residuals

2015 ◽  
Author(s):  
Mortuza Ali ◽  
Manzur Murshed ◽  
Shampa Shahriyar ◽  
Manoranjan Paul
Keyword(s):  
Image Coding ◽  
Binary Tree ◽  
Tree Decomposition
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