Using diode-stacked NMOS as high voltage tolerant ESD protection device for analog applications in deep submicron CMOS technologies
2003 ◽
Vol 47
(5)
◽
pp. 865-871
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2009 ◽
Vol 40
(6)
◽
pp. 1007-1012
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2009 ◽
Vol E92-C
(9)
◽
pp. 1188-1193
2005 ◽
Vol E88-C
(3)
◽
pp. 429-436
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2019 ◽
Vol 66
(7)
◽
pp. 2884-2891
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1999 ◽
Vol 43
(2)
◽
pp. 375-393
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Keyword(s):
2020 ◽
Vol E103.C
(4)
◽
pp. 191-193
Keyword(s):