Introducing disjoint spectral translation in spectral multiple-valued logic design

1978 ◽  
Vol 14 (8) ◽  
pp. 241 ◽  
Author(s):  
Claudio Moraga
Keyword(s):  
Logic Design ◽  
Multiple Valued Logic ◽  
Spectral Translation

Voltage-controlled multiple-valued logic design using negative differential resistance devices

2010 ◽  
Vol 54 (12) ◽  
pp. 1637-1640 ◽  
Author(s):  
Kwang-Jow Gan ◽  
Cher-Shiung Tsai ◽  
Yan-Wun Chen ◽  
Wen-Kuan Yeh
Keyword(s):  
Negative Differential Resistance ◽  
Differential Resistance ◽  
Logic Design ◽  
Multiple Valued Logic

CMOS multiple-valued logic design. I. Circuit implementation

1993 ◽  
Vol 40 (8) ◽  
pp. 503-514 ◽  
Author(s):  
A.K. Jain ◽  
R.J. Bolton ◽  
M.H. Abd-El-Barr
Keyword(s):  
Logic Design ◽  
Circuit Implementation ◽  
Multiple Valued Logic

Conquering Uncertainty in Multiple-Valued Logic Design

2004 ◽  
pp. 259-283
Author(s):  
Denis V. Popel
Keyword(s):  
Logic Design ◽  
Multiple Valued Logic

Parameter spectrum in spectral multiple-valued logic design

1983 ◽  
Vol 19 (6) ◽  
pp. 199 ◽  
Author(s):  
Gongli Zhang
Keyword(s):  
Logic Design ◽  
Multiple Valued Logic

Conquering Uncertainty in Multiple-Valued Logic Design

2003 ◽  
Vol 20 (3/4) ◽  
pp. 419-443 ◽  
Author(s):  
Denis V. Popel
Keyword(s):  
Logic Design ◽  
Multiple Valued Logic

Multiple-valued logic design: an introduction

2017 ◽  
Author(s):  
George Epstein
Keyword(s):  
Logic Design ◽  
Multiple Valued Logic

scholarly journals Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 12 ◽  
Author(s):  
Elena Zaitseva ◽  
Vitaly Levashenko ◽  
Igor Lukyanchuk ◽  
Jan Rabcan ◽  
Miroslav Kvassay ◽  
...  
Keyword(s):  
New Technologies ◽  
Fundamental Principle ◽  
Logic Design ◽  
Stable States ◽  
Programmable Logic Arrays ◽  
Atomic Size ◽  
Multiple Valued Logic ◽  
Logic Block ◽  
Binary Information ◽  
A New Technique

Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed–Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression’s construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.

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