scholarly journals Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 12 ◽  
Author(s):  
Elena Zaitseva ◽  
Vitaly Levashenko ◽  
Igor Lukyanchuk ◽  
Jan Rabcan ◽  
Miroslav Kvassay ◽  
...  
Keyword(s):  
New Technologies ◽  
Fundamental Principle ◽  
Logic Design ◽  
Stable States ◽  
Programmable Logic Arrays ◽  
Atomic Size ◽  
Multiple Valued Logic ◽  
Logic Block ◽  
Binary Information ◽  
A New Technique

Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed–Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression’s construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.

Voltage-controlled multiple-valued logic design using negative differential resistance devices

2010 ◽  
Vol 54 (12) ◽  
pp. 1637-1640 ◽  
Author(s):  
Kwang-Jow Gan ◽  
Cher-Shiung Tsai ◽  
Yan-Wun Chen ◽  
Wen-Kuan Yeh
Keyword(s):  
Negative Differential Resistance ◽  
Differential Resistance ◽  
Logic Design ◽  
Multiple Valued Logic

CMOS multiple-valued logic design. I. Circuit implementation

1993 ◽  
Vol 40 (8) ◽  
pp. 503-514 ◽  
Author(s):  
A.K. Jain ◽  
R.J. Bolton ◽  
M.H. Abd-El-Barr
Keyword(s):  
Logic Design ◽  
Circuit Implementation ◽  
Multiple Valued Logic

Conquering Uncertainty in Multiple-Valued Logic Design

2004 ◽  
pp. 259-283
Author(s):  
Denis V. Popel
Keyword(s):  
Logic Design ◽  
Multiple Valued Logic

Parameter spectrum in spectral multiple-valued logic design

1983 ◽  
Vol 19 (6) ◽  
pp. 199 ◽  
Author(s):  
Gongli Zhang
Keyword(s):  
Logic Design ◽  
Multiple Valued Logic

A graph representation for programmable logic arrays to facilitate testing and logic design

1998 ◽  
Vol 17 (10) ◽  
pp. 1030-1043
Author(s):  
Jing-Jou Tang ◽  
Kuen-Jong Lee ◽  
Bin-Da Liu
Keyword(s):  
Graph Representation ◽  
Logic Design ◽  
Programmable Logic ◽  
Programmable Logic Arrays

Conquering Uncertainty in Multiple-Valued Logic Design

2003 ◽  
Vol 20 (3/4) ◽  
pp. 419-443 ◽  
Author(s):  
Denis V. Popel
Keyword(s):  
Logic Design ◽  
Multiple Valued Logic

Multiple-valued logic and optimization of programmable logic arrays

Computer ◽  
10.1109/2.52 ◽  
1988 ◽  
Vol 21 (4) ◽  
pp. 71-80 ◽  
Author(s):  
T. Sasao
Keyword(s):  
Programmable Logic ◽  
Programmable Logic Arrays ◽  
Multiple Valued Logic

scholarly journals Foundations for Applications of Gibbs Derivatives in Logic Design and VLSI

VLSI Design ◽  
2002 ◽  
Vol 14 (1) ◽  
pp. 65-81 ◽  
Author(s):  
Radomir S. Stanković ◽  
Milena Stanković ◽  
Reiner Creutzburg
Keyword(s):  
New Technologies ◽  
Differential Operators ◽  
Rate Of Change ◽  
Logic Design ◽  
Logic Function ◽  
Spectral Techniques ◽  
Cad Systems ◽  
Vlsi Cad ◽  
Efficient Calculation ◽  
Logic Functions

New technologies and increased requirements for performances of digital systems require new mathematical theories and tools as a basis for future VLSI CAD systems. New or alternative mathematical approaches and concepts must be suitable to solve some concrete problems in VLSI and efficient algorithms for their efficient application should be provided. This paper is an attempt in this direction and relates with the recently renewed interest in arithmetic expressions for switching functions, instead representations in Boolean structures, and spectral techniques and differential operators in switching theory and applications. Logic derivatives are efficiently used in solving different tasks in logic design, as for example, fault detection, functional decomposition, detection of symmetries and co-symmetries of logic functions, etc. Their application is based on the property that by differential operators, we can measure the rate of change of a logic function. However, by logic derivatives, we can hardly distinguish the direction of the change of the function, since they are defined in finite algebraic structures. Gibbs derivatives are a class of differential operators on groups, which applied to logic functions, permit to overcome this disadvantage of logic derivatives. Therefore, they may be useful in logic design in the same areas where the logic derivatives have been already using. For such applications, it is important to provide fast algorithms for calculation of Gibbs derivatives on finite groups efficiently in terms of space and time. In this paper, we discuss the methods for efficient calculation of Gibbs derivatives. These methods should represent a basis for further applications of these and related operators in VLSI CAD systems.

An Efficient Scheduling Technique for Biological Sequence Alignment

2015 ◽  
Vol 754-755 ◽  
pp. 1087-1092
Author(s):  
Mohd Nazrin Md Isa ◽  
Sohiful Anuar Zainol Murad ◽  
Mohamad Imran Ahmad ◽  
Muhammad M. Ramli ◽  
Rizalafande Che Ismail
Keyword(s):  
Sequence Alignment ◽  
Substitution Matrix ◽  
Processing Element ◽  
Biological Sequence ◽  
Matrix Computation ◽  
Logic Block ◽  
Order Of Magnitude ◽  
Speed Up ◽  
A New Technique ◽  
Protein Sequencer

Computing alignment matrix score to search for regions of homology between biological sequences is time consuming task. This is due to the recursive nature of the dynamic programming-based algorithms such as the Smith-Waterman and the Needleman-Wunsch algorithmns. Typical FPGA-based protein sequencer comprises of two main logic blocks. One for computing alignment scores i.e. the processing element (PE), while another logic block for configuring the PE with coefficients. During alignment matrix computation, the logic block for configuring the PE are left unused until the time consuming alignment matrix computation finished. Therefore, a new technique, known as overlap computation and configuration (OCC) is proposed to minimize the time overhead for performing biological sequence alignment. The OCC technique simultaneously updating substitution matrix in a processing element (PE) systolic array, while computing alignment matrix scores. Results showed that, the sequencer achieves more than two order of magnitude speed-up higher compared to the state of the art, at negligible area overhead, if any.

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