n-scroll chaos generators: a simple circuit model

2001 ◽  
Vol 37 (3) ◽  
pp. 147 ◽  
Author(s):  
M.E. Yalçin ◽  
S. Özoğuz ◽  
J.A.K. Suykens ◽  
J. Vandewalle
Keyword(s):  
Circuit Model ◽  
Simple Circuit

Metal Bridge Defects Localization by a Tiny Leakage between One of Bridged Signals and VDD (GND)

2014 ◽  
Author(s):  
Chunlei Wu ◽  
Suying Yao
Keyword(s):  
Circuit Model ◽  
Functional Modules ◽  
Semiconductor Technology ◽  
Simple Circuit ◽  
Lock In

Abstract As semiconductor technology continues to advance to smaller dimensions and more complex circuit designs, it is becoming more challenging to locate the resistive short directly between two metal lines (signals) due to a metal bridge defect. Especially these two metal lines are very long and relevant to many functional modules. After studying the failed circuit model, we found there should be a tiny leakage between one of the bridged signals and one of common power signals (such as VDD and GND) on a failed IC compared with the reference one, if there is a metal bridge defect between these two bridged signals. The tiny leakage between one of the bridged signals and one of power signals is an indirect leakage that is a mapping of the direct resistive short between these two bridged signals. The metal bridge defect could be pinpointed with the tiny leakage between one of the bridged signals and one of power signals by Lock-in IR-OBIRCH. It is an easier and faster way to locate the metal bridge defects. In this paper, the basic and simple circuit model with a metal bridge defect will be presented and two cases will be studied to demonstrate how to localize a metal bridge defect by the tiny leakage between one of the bridged signals and one of power signals.

Power/Ground Pin-Map Design for Power Integrity

2011 ◽  
Author(s):  
Jingook Kim ◽  
James Drewniak ◽  
Jun Fan
Keyword(s):  
High Speed ◽  
Ground Plane ◽  
Resonant Cavity ◽  
Circuit Model ◽  
Cavity Model ◽  
Power Integrity ◽  
Simple Circuit ◽  
Parasitic Inductance ◽  
Map Design ◽  
Multiple Power

In this paper, a simple circuit model for IC multiple power and ground via arrays in a multilayer PCB is built based on the resonant cavity model. Using the circuit model, the parasitic inductance for the IC power and ground connection is quantitatively investigated according to via number and via patterns. The stack-up configuration of the power/ground plane pair is not critical for PDN performance in multilayer PCBs, as long as there are sufficient IC power/ground vias in an alternating pattern. The outcome of this work can be used to guide the pin-map design for high-speed packages.

scholarly journals Simple circuit model of SiC pin diode composed by using experimental electrical characteristics

2005 ◽  
Vol 2 (13) ◽  
pp. 392-398 ◽  
Author(s):  
Katsunori Asano ◽  
Tsuyoshi Funaki ◽  
Yoshitaka Sugawara ◽  
Takashi Hikihara
Keyword(s):  
Circuit Model ◽  
Pin Diode ◽  
Electrical Characteristics ◽  
Simple Circuit
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