Scalable Microsprings for Integrated Test and Packaging

Lithographically defined spring electrical contacts have many applications for next generation electronics test and packaging. The springs can lower the cost of multi-chip modules because their rework ability addresses the known-good-die problem. Lower height chip stacking for mobile electronics markets is enabled because a sliding spring can have a much shorter profile than solder. Larger die can be directly bonded to the board because the compliance absorbs thermal expansion mismatches between substrates. Significant stress isolation is possible, which is important for mechanically sensitive die such as MEMS and low K die. Very high density is possible, as 6 (am pitch has been demonstrated. Fabrication is scalable and assembly is low temperature. This paper reviews our prototype demonstrations for these applications as well as relevant reliability data and contact studies.

Reliability Studies for Package-on-Package Components in Drop and Shock Environments

The consumer electronics industry stands at a critical juncture where manufacturers strive to incorporate more functionality in smaller packages. In the highly competitive consumer electronics market, a continued demand for products with smallest possible form-factor yet high functionality has led to the proliferation of 3D packaging technologies. Package-on-Package (PoP) architectures, in particular have attracted a lot of interest, especially in portable electronics industry. The advantages of these stacked 3D architectures include simplified and compact design, savings of board space allowing for more package landings, reduced pin counts and optimized production costs. While a lot of recent research, in the field of PoP architectures has been focused on development of optimum process flows and warpage control during reflow, the effects of reflow parameters on the quality of PoP build and the associated reflow defects including warpage have not been extensively researched. Additionally, studies on reliability issues associated with PoP assemblies in drop and shock environments are scarce. Since PoP architectures find their applications mainly in portable electronics, which are susceptible to frequent drops and careless handling at the hand of the consumer, the reliability of PoP architectures in environments representative of the real world is critical to their success in the industry. In this study, Single component PoP test vehicles have been fabricated as per JEDEC standards for quantifying the reliability of PoP packages in drop and shock. Daisy chained double-stack PoP components have been used to identify failure for subsequent drop/shock performance analysis. Experimental strain data acquired using Digital Image Correlation and high speed continuity data- for identifying failure has been used in conjunction with validated FE simulations of drop test events; for development of life prediction models for PoP architectures. Validated node based global-local FE simulations are used to predict strains in critical solder balls in both layers of the PoP stack. The drop/shock reliability studies and life prediction models presented in this work, present an insight into PoP failures and eliminate the need for exhaustive testing procedures.

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps

Since the thickness of the stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the thermal residual stress distribution appears in the stacked chips due to the periodic alignment of metallic bumps, and they deteriorate the reliability of products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of 4 gauges with different crystallographic directions. This alignment of strain gauges enables to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made by silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper layer was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the rigid joint formation by alloying with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed experimentally that both the hound’s-tooth alignment between a TSV (Through Silicon Via) and a bump and control of mechanical properties of electroplated copper thin films used for the TSV and bump is indispensable in order to minimize the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process induced stress in 3D stacked chips quantitatively.

Precision Evaluation for Thermal Fatigue Life of Power Module Using Coupled Electrical-Thermal-Structural Analysis

For power module, the reliability evaluation of thermal fatigue life by power cycling has been prioritized as an important concern. Since in power cycling produces there exists non-uniform temperature distribution in the power module, coupled thermal-structure analysis is required to evaluate thermal fatigue mechanism. The thermal expansion difference between a Si chip and a substrate causes thermal fatigue. In this study, thermal fatigue life of solder joints on power module was evaluated. The finite element method (FEM) was used to evaluate temperature distribution induced by joule heating. Higher temperature appears below the Al wire because the electric current flows through the bonding Al wire. Coupled thermal-structure analysis is also required to evaluate the inelastic strain distribution. The damage of each part of solder joint can be calculated from equivalent inelastic strain range and crack propagation was simulated by deleting damaged elements step by step. The initial cracks were caused below the bonding Al wire and propagated concentrically under power cycling. There is the difference from environmental thermal cycling where the crack initiated at the edge of solder layer. In addition, in order to accurately evaluate the thermal fatigue life, the factors affecting the thermal fatigue life of solder joint where verified using coupled electrical-thermal-structural analysis. Then, the relation between the thermal fatigue life of solder joint and each factor is clarified. The precision evaluation for the thermal fatigue life of power module is improved.

Study on High Reliability of Lead-Free Solder Joint on Metal Substrate

This paper proposes the high reliable design method for lead-free solder joint on metal substrate on chip component. First, the crack propagation analysis method for estimating rupture life of solder joint was constructed. And then, the effect of material properties of insulating layer on metal substrate and solder joint shape for rupture life of solder joint was evaluated using crack propagation analysis. As the result, the relation between young’s modulus of insulating layer and rupture life was indicated quantitatively. Also, the relation of filet length for rupture life of solder joint was evaluated. Secondary, evaluation method of heat dissipation for metal substrate was proposed. Because thermal conductivity of insulating layer affects temperature rise of heating device. And, the relation between thermal conductivity of insulating layer and temperature rise of heating device was indicated.

Thermal Conductivity Reduction in Few-Layer Graphene

Using the linearized Boltzmann transport equation and perturbation theory, we analyze the reduction in the intrinsic thermal conductivity of few-layer graphene sheets accounting for all possible three-phonon scattering events. Even with weak coupling between layers, a significant reduction in the thermal conductivity of the out-of-plane acoustic modes is apparent. The main effect of this weak coupling is to open many new three-phonon scattering channels that are otherwise absent in graphene. The highly restrictive selection rule that leads to a high thermal conductivity of ZA phonons in single-layer graphene is only weakly broken with the addition of multiple layers, and ZA phonons still dominate thermal conductivity. We also find that the decrease in thermal conductivity is mainly caused by decreased contributions of the higher-order overtones of the fundamental out-of-plane acoustic mode. Moreover, the extent of reduction is largest when going from single to bilayer graphene and saturates for four layers. The results compare remarkably well over the entire temperature range with measurements of of graphene and graphite.

Design, Reliability and Manufacturing Readiness for MEMS Microphone

Microphone is a critical component for seamless communication converting an acoustic signal (vocal) to an electrical signal. Traditionally Electrets Condenser Microphones (ECM) have been the primary proponent of audio component in many consumer products. With functionally rich consumer devices (example smart phones, etc) there is a growing trend to look at components with higher functionality but a smaller form factor. Microelectronic Mechanical Systems (MEMS) microphone is seen as a possible replacement to ECM due to its significant reduction in form fit with additional functionality. The paper is an effort to illustrate steps that can be considered while designing MEMS microphone in a system. This includes Design considerations, Reliability tests, Manufacturing challenges and Readiness to ensure higher yield during the final assembly. Manufacturing issues (Top 5) and guideline presented in the paper are not just to increase the assembly yield (system level), but also to increase an awareness upfront to the design phase to help create a robust system/product.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Joule Heat Welding of Thin Metallic Wires and Thermoelectric Effects Around Dissimilar Metal Weld

Fine thermoelectric elements were fabricated on an electrode chip where the tips of the Pt and W thin wires having the diameter of 5 μm were welded together by Joule heat welding. Firstly, the dissimilar metal weld was contacted to thin wire heater and the voltage appeared in the circuit due to Seebeck effect was measured. Current was supplied to the one of the thermoelectric element and the temperature at the Pt/W weld was measured by the other element. It was found that the temperature at dissimilar metal weld depended on the direction of current and Peltier effect was successfully observed.

Optimizing System-on-Film (SOF) Design Using Finite Element Analysis

System-On-Film (SOF) module is a complex integration of a fine pitch high density die and surface mounted discrete devices on a polyimide (PI) film laminate. The die is connected to the film using a thermo-compression flip-chip bonding (TCB) process which is capable of providing a very high density interconnect at less than 50um pitch. Several design and bonding parameters have to be controlled in order to achieve a reliable bond between the Au bumps on the die and the Sn plated Cu traces on the PI film. In the current work, the TCB process is studied using Finite Element Analysis (FEA) to optimize the design parameters and assure proper process margins. The resultant forces acting on the bump-to-trace interfaces are quantified across the different potential geometrical combinations. Baseline simulations showed higher stresses on specific bump locations and stress gradients acting on the bumps along the different sides of the die. These observations were correlated to both the failures and near failures on the actual test vehicles. Further simulations were then utilized to optimize and navigate design tradeoffs at both the die and flexible substrate design levels for a more robust design solution. Construction analysis performed on parts built using optimized design parameters showed significant improvements and correlated well with the simulation results.