Thin-Film-Based SAW Magnetic Field Sensors

In this work, the first surface acoustic-wave-based magnetic field sensor using thin-film AlScN as piezoelectric material deposited on a silicon substrate is presented. The fabrication is based on standard semiconductor technology. The acoustically active area consists of an AlScN layer that can be excited with interdigital transducers, a smoothing SiO2 layer, and a magnetostrictive FeCoSiB film. The detection limit of this sensor is 2.4 nT/Hz at 10 Hz and 72 pT/Hz at 10 kHz at an input power of 20 dBm. The dynamic range was found to span from about ±1.7 mT to the corresponding limit of detection, leading to an interval of about 8 orders of magnitude. Fabrication, achieved sensitivity, and noise floor of the sensors are presented.

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

Microwave core-chips are highly integrated MMICs that are in charge of all the beam-shaping functions of a transmit-receive module within a phased array system. Such chips include switches, amplifiers and attenuators, phase shifters, and possibly other elements, each to be controlled by external digital signals. Given the large number of control lines to be integrated in a core-chip, the embedding of a serial to parallel interface is indispensable. Digital design in compound semiconductor technology is still rather challenging due to the absence of complementary devices and the availability of a limited number of metallization layers. Moreover, in large arrays, high chip yield and repeatability are required. This paper discusses and compares challenges and solutions for the key sub-circuits of GaAs serial to parallel converters for core-chip applications, reviewing the pros and cons of the different implementations proposed in the literature.

Crystallization of Bi-substituted iron garnet bi-layers

Magneto-optical (MO) structures are widely used for different application in the fields of magnetoplasmonics, magneto-optics, photonics e.t.c. Bi-substituted iron garnet (Bi:IG) is high-performance MO material. Integration of Bi:IG films to silicon semiconductor technology gives new opportunities to create nanoscale hight performance MO devices. Vacuum sputtering deposition allows to fabricate Bi:IG structures on different substrate types. Authors investigate crystallization process of Bi:IG bi-layers in a different process parameter (different layers composition and its thickness, temperature and time of annealing) using gadolinium gallium garnet GGG and fused quartz SiO2 substrates to determine dependences which impact on crystallization.

ITO-free Perovskite Light-Emitting Electrochemical Cell

Since Complementary metal–oxide–semiconductor technology is the conventional technology for micro- and optoelectronics, integration of emerging materials, such as halide perovskites, into the process is an important branch of perovskite technologies development. In this regard ITO free device research becomes increasingly important. The Perovskite Light-Emitting electrochemical cells are a promising alternative to conventional Perovskite Light Emitting Diodes. In this work we demonstrate green (λEL = 523 nm) CsPbBr3 Perovskite Light-Emitting electrochemical cells with luminescence intensity of 50 kd/m2 integrated with Si++(111) substrate.

Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 µm depth embedded in 0.18 µm CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.