Energy-aware instruction cache design using small trace cache

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2009.0049 ◽

2010 ◽

Vol 4 (4) ◽

pp. 293-305 ◽

Author(s):

J.M. Kim ◽

C.H. Kim ◽

S.W. Chung

Keyword(s):

Energy Aware ◽

Instruction Cache ◽

Trace Cache ◽

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Instruction Cache Design for Energy-Aware Embedded Processors by Using Backward Branch Information

2007 International Symposium on Information Technology Convergence (ISITC 2007) ◽

10.1109/isitc.2007.36 ◽

2007 ◽

Author(s):

Cheol Hong Kim ◽

Wontaek Lim ◽

Toan Nguyen ◽

Deokjai Choi ◽

Gueesang Lee

Keyword(s):

Embedded Processors ◽

Energy Aware ◽

Instruction Cache ◽

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First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption

Lecture Notes in Computer Science - Embedded Computer Systems: Architectures, Modeling, and Simulation ◽

10.1007/11512622_12 ◽

2005 ◽

pp. 103-111 ◽

Author(s):

Cheol Hong Kim ◽

Sunghoon Shim ◽

Jong Wook Kwak ◽

Sung Woo Chung ◽

Chu Shik Jhon

Keyword(s):

Energy Consumption ◽

Instruction Cache ◽

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Instruction cache design space exploration for embedded software applications

2015 19th International Symposium on VLSI Design and Test ◽

10.1109/isvdat.2015.7208127 ◽

2015 ◽

Author(s):

Rajendra Patel ◽

Arvind Rajawat

Keyword(s):

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Embedded Software ◽

Instruction Cache ◽

Software Applications ◽

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A Low-Power Instruction Cache Design Based on Record Buffer

Journal of Computer Research and Development ◽

10.1360/crad20060426 ◽

2006 ◽

Vol 43 (4) ◽

pp. 744

Author(s):

Zhiqiang Ma

Keyword(s):

Low Power ◽

Instruction Cache ◽

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Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors

2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2017.8016154 ◽

2017 ◽

Author(s):

Fatemeh Arezoomand ◽

Arghavan Asad ◽

Mahdi Fazeli ◽

Mahmood Fathy ◽

Farah Mohammadi

Keyword(s):

Chip Multiprocessors ◽

Energy Aware ◽

Cache Design ◽

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Low power instruction cache design based on branch execution tracks

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811822 ◽

2013 ◽

Author(s):

Quanquan Li ◽

Qi Wang ◽

Tiejun Zhang ◽

Donghui Wang ◽

Chaohuan Hou

Keyword(s):

Low Power ◽

Instruction Cache ◽

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A CASE STUDY OF ENERGY-EFFICIENT LOOP INSTRUCTION CACHE DESIGN FOR EMBEDDED MULTITASKING SYSTEMS

Proceedings of the 1st International Conference on Smart Grids and Green IT Systems ◽

10.5220/0003951001970202 ◽

2012 ◽

Keyword(s):

Energy Efficient ◽

Instruction Cache ◽

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EMC: Energy-Aware Morphable Cache Design for Non-Volatile Processors

IEEE Transactions on Computers ◽

10.1109/tc.2018.2879103 ◽

2019 ◽

Vol 68 (4) ◽

pp. 498-509 ◽

Author(s):

Weining Song ◽

Yang Zhou ◽

Mengying Zhao ◽

Lei Ju ◽

Chun Jason Xue ◽

...

Keyword(s):

Energy Aware ◽

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A Runtime Auto Scalable Power-Efficient Instruction-Cache Design

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1465824 ◽

2005 ◽

Author(s):

Tay Teng Tiow ◽

Zhu Xiaoping

Keyword(s):

Power Efficient ◽

Instruction Cache ◽

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Variable-sized object packing and its applications to instruction cache design

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2008.04.002 ◽

2008 ◽

Vol 34 (5) ◽

pp. 438-444 ◽

Author(s):

Rung-Bin Lin

Keyword(s):

Instruction Cache ◽

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