Leakage power analysis and reduction for nano-scale circuits

System-on-Chip: Next Generation Electronics ◽

10.1049/pbcs018e_ch13 ◽

2011 ◽

pp. 415-448 ◽

Cited By ~ 1

Author(s):

Amit Agarwal ◽

Saibal Mukhopadhyay ◽

Chris Kim ◽

Arijit Raychowdhury ◽

Kaushik Roy

Keyword(s):

Power Analysis ◽

Leakage Power ◽

Nano Scale

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Leakage Power Analysis attacks: Theoretical analysis and impact of variations

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) ◽

10.1109/icecs.2009.5410929 ◽

2009 ◽

Cited By ~ 3

Author(s):

M. Alioto ◽

L. Giancane ◽

G. Scotti ◽

A. Trifiletti

Keyword(s):

Theoretical Analysis ◽

Power Analysis ◽

Leakage Power ◽

Power Analysis Attacks

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Cache leakage power analysis in embedded applications

The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. ◽

10.1109/mwscas.2004.1354209 ◽

2004 ◽

Cited By ~ 1

Author(s):

D. Kudithipudi ◽

S. Petko ◽

E. John

Keyword(s):

Power Analysis ◽

Leakage Power ◽

Embedded Applications

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Development of Junction Temperature Decision (JTD) Map for Thermal Design of Nano-scale Devices Considering Leakage Power

Twenty-Third Annual IEEE Semiconductor Thermal Measurement and Management Symposium ◽

10.1109/stherm.2007.352407 ◽

2007 ◽

Author(s):

Yunhyeok Im ◽

Eun Seok Cho ◽

Kiwon Choi ◽

Sayoon Kang

Keyword(s):

Leakage Power ◽

Thermal Design ◽

Junction Temperature ◽

Nano Scale

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A new Nano-scale differential logic style for power analysis attack

2015 23rd Iranian Conference on Electrical Engineering ◽

10.1109/iraniancee.2015.7146283 ◽

2015 ◽

Author(s):

Omid Abdi ◽

Ali Jahanian

Keyword(s):

Power Analysis ◽

Nano Scale ◽

Power Analysis Attack

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Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits

IEEE Transactions on Electron Devices ◽

10.1109/ted.2005.846317 ◽

2005 ◽

Vol 52 (5) ◽

pp. 980-986 ◽

Cited By ~ 31

Author(s):

K. Kim ◽

K.K. Das ◽

R.V. Joshi ◽

C.T. Chuang

Keyword(s):

Power Analysis ◽

Leakage Power ◽

Double Gate

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Leakage power analysis and reduction: models, estimation and tools

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:20045084 ◽

2005 ◽

Vol 152 (3) ◽

pp. 353 ◽

Cited By ~ 43

Author(s):

A. Agarwal ◽

S. Mukhopadhyay ◽

C.H. Kim ◽

A. Raychowdhury ◽

K. Roy

Keyword(s):

Power Analysis ◽

Leakage Power

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Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.l1006.10812s219 ◽

2019 ◽

Vol 8 (12S2) ◽

pp. 27-30

Keyword(s):

Power Consumption ◽

Low Power ◽

Power Dissipation ◽

Power Analysis ◽

Research Work ◽

Leakage Power ◽

Total Power ◽

Voltage Supply ◽

Field Programmable ◽

Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

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