scholarly journals Research on Spacecraft Integrated Electronic System Architecture Based on Information Fusion

2018 ◽  
Vol 228 ◽  
pp. 01018 ◽  
Author(s):  
Qiang Ji ◽  
Shifeng Zhang ◽  
Haoguang Zhao
Keyword(s):  
Information Fusion ◽  
System Architecture ◽  
Electronic System ◽  
Satellite System ◽  
Transport Layer ◽  
Data Systems ◽  
Consultative Committee ◽  
Application Layer ◽  
Space Data ◽  
Protocol Architecture

This paper has designed the integrated electronic system and protocol architecture based on the standard of Consultative Committee for Space Data Systems (CCSDS) and European Communication Satellite System (ECSS). The application layer, application support layer, transport layer and sub network layer in the architecture can be described in detail, and the functions can be realized through the combination of various business and protocols. The architecture can provide technical support for the intellectualization and networking of spacecraft, standardize the spacecraft interface and protocol, it can promote the generalization of spacecraft equipment and software, and provide more flexible and powerful functions for the spacecraft.

scholarly journals Satellite Image Compression using RICE Algorithm

2019 ◽  
Vol 8 (2) ◽  
pp. 1082-1085
Keyword(s):  
Satellite Images ◽  
Satellite Image ◽  
Data Systems ◽  
Consultative Committee ◽  
Compression Scheme ◽  
Compression Algorithms ◽  
The Earth ◽  
Variable Length Codes ◽  
Active Research ◽  
Space Data

Processing of satellite images is time-intensive owing to the large surface of the earth and the necessity for high resolution. Compression algorithms are an active research topic since there is no single algorithm which can achieve the best compression at the highest speed. Different compression algorithms need to be explored to enhance the speed of the analysis. Here, a lossless compression scheme using RICE algorithm is implemented using Matlab and Verilog on a satellite image according to the CCSDS (Consultative Committee for Space Data Systems) recommendation. The RICE algorithm uses a set of variable length codes. The architecture comprises of a Pre-processor, Adaptive entropy coder, Postprocessor and an Inverse mapper. The design has been implemented using Xilinx.

Research of Three-Dimensional Layered Network Architecture LDM3 for ITS

2015 ◽  
Vol 719-720 ◽  
pp. 791-797
Author(s):  
Ya Duan Ruan ◽  
Xiang Jun Chen ◽  
Qi Mei Chen
Keyword(s):  
Information Fusion ◽  
Network Architecture ◽  
Intelligent Transportation System ◽  
Three Dimensional ◽  
Transport Layer ◽  
Massive Data ◽  
Local Dynamic ◽  
Application Layer ◽  
Application Systems ◽  
Dynamic Map

As Intelligent Transportation System (ITS) grows increasingly in size and complexity, the issues on how to improve interoperability and the performance of processing massive data become more critical. This paper proposes a new three-dimensional layered network architecture called Local Dynamic Map/Multimedia/Management (LDM3) to address these issues. In LDM3, the three-dimensional architecture consists of the information fusion layer newly introduced, as well as the application layer and transport layer. The primitive mechanism defined in the architecture improves the efficiency of the communication of network elements in such heterogeneous network system. By using the standardized format of message and data, the application systems can get desired information pushed by information fusion layer, instead of processing data from all kinds of sensors. This mechanism improves the effectiveness of the whole system significantly by avoiding duplicate work on different application systems. Meanwhile, the workload and the hardware requirement for application systems are relieved. We apply LDM3in the demonstration project for traffic Internet Of Things (IOT) in Jiangsu province. The result shows LDM3is an effective and efficient solution for ITS.

Implementation of a New LDPC Encoder for CCSDS Specification Based on FPGA

2013 ◽  
Vol 816-817 ◽  
pp. 981-984
Author(s):  
Zheng Zheng ◽  
Peng Zhang ◽  
Chang Yin Liu
Keyword(s):  
Power Consumption ◽  
Type I ◽  
Low Density ◽  
Data Systems ◽  
Parity Check ◽  
Consultative Committee ◽  
Serial Output ◽  
Low Density Parity Check ◽  
Memory Resource ◽  
Space Data

A new Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) encoder based on type I Rotate-Left-Accumulator (RLA) circuits is designed for the Consultative Committee for Space Data Systems (CCSDS). The proposed encoder is serial-input and serial-output. It can reduce the power consumption and save memory resource. FPGA simulation shows its feasibility.

scholarly journals IMPLEMENTASI ENCODER REED-SOLOMON PADA FPGA BERBASIS CCSDS (REED-SOLOMON ENCODER IMPLEMENTATION ON FPGA BASED ON CCSDS)

2015 ◽  
Vol 12 (2) ◽  
Author(s):  
Patria Rachman Hakim ◽  
Abdul Rahman ◽  
Deddy El Amin ◽  
Widya Roza ◽  
Elvira Rahim
Keyword(s):  
Channel Coding ◽  
Field Programmable Gate Array ◽  
Data Handling ◽  
Data Systems ◽  
Consultative Committee ◽  
Ip Core ◽  
Field Programmable ◽  
Gate Array ◽  
Space Data

Salah satu fungsi sistem Payload Data Handling (PDH) pada sebuah satelit adalah melakukan channel coding untuk data citra satelit. Consultative Committee for Space Data Systems (CCSDS) telah merekomendasikan penggunaan encoder Reed-Solomon (RS) untuk keperluan channel coding tersebut. Untuk dapat merealisasikan transmisi dengan laju data yang tinggi, maka implementasi algoritma encoder RS pada sitem PDH satelit membutuhkan Field Programmable Gate Array (FPGA). Penelitian ini bertujuan untuk merancang modul encoder RS(255,223) berbasis CCSDS dan mengimplementasikan encoder tersebut pada FPGA dengan desain rangkaian yang lebih optimal dibandingkan dengan encoder RS komersial (IP-core). Berdasarkan hasil pengujian yang telah dilakukan, encoder yang dirancang memiliki beberapa kelebihan dalam hal efisiensi gerbang logika yang digunakan dan tingkat kinerja data keluaran yang dihasilkan. Selain itu, pada penelitian ini juga dikembangkan metode encoding paralel yang akan diterapkan pada sistem PDH satelit. Hasil pengujian menunjukkan bahwa dengan menggunakan metode tersebut, data keluaran yang dihasilkan encoder memiliki laju data yang lebih tinggi dan tidak membutuhkan data dummy untuk melengkapi data keluaran. Kedua hasil tersebut diharapkan dapat mendukung pengembangan sistem PDH satelit yang dilakukan di Pusat Teknologi Satelit saat ini.Kata kunci: Channel coding, Encoder Reed-Solomon, PDH, FPGA, CCSDS

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