Nonvolatile field programmable spin-logic for reconfigurable computing

2002 ◽  
Vol 80 (7) ◽  
pp. 1291-1293 ◽  
Author(s):  
R. Richter ◽  
L. Bär ◽  
J. Wecker ◽  
G. Reiss
Keyword(s):  
Reconfigurable Computing ◽  
Spin Logic ◽  
Field Programmable

scholarly journals Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures

2010 ◽  
Vol 2010 ◽  
pp. 1-16 ◽  
Author(s):  
James Coole ◽  
Greg Stitt
Keyword(s):  
Data Structures ◽  
Reconfigurable Computing ◽  
Application Development ◽  
Sequential Memory ◽  
Generalized Framework ◽  
Field Programmable ◽  
Order Of Magnitude ◽  
Programmable Gate Arrays ◽  
Irregular Data ◽  
Access Patterns

Field-programmable gate arrays (FPGAs) and other reconfigurable computing (RC) devices have been widely shown to have numerous advantages including order of magnitude performance and power improvements compared to microprocessors for some applications. Unfortunately, FPGA usage has largely been limited to applications exhibiting sequential memory access patterns, thereby prohibiting acceleration of important applications with irregular patterns (e.g., pointer-based data structures). In this paper, we present a design pattern for RC application development that serializes irregular data structure traversals online into a traversal cache, which allows the corresponding data to be efficiently streamed to the FPGA. The paper presents a generalized framework that benefits applications with repeated traversals, which we show can achieve between 7x and 29x speedup over pointer-based software. For applications without strictly repeated traversals, we present application-specialized extensions that benefit applications with highly similar traversals by exploiting similarity to improve memory bandwidth and execute multiple traversals in parallel. We show that these extensions can achieve a speedup between 11x and 70x on a Virtex4 LX100 for Barnes-Hut n-body simulation.

Tunneling systems for field programmable spin-logic gates

2002 ◽  
Vol 91 (10) ◽  
pp. 8402 ◽  
Author(s):  
R. Richter ◽  
L. Bär ◽  
J. Wecker ◽  
G. Reiss
Keyword(s):  
Logic Gates ◽  
Spin Logic ◽  
Field Programmable

Electronic Hardware for Fuzzy Computation

2010 ◽  
pp. 1-30 ◽  
Author(s):  
Koldo Basterretxea ◽  
Inés del Campo
Keyword(s):  
Data Mining ◽  
Reconfigurable Computing ◽  
High Performance ◽  
Reconfigurable Hardware ◽  
Dynamic Partial Reconfiguration ◽  
Field Programmable ◽  
Analog Approach ◽  
Programmable Gate Arrays ◽  
System On Programmable Chip ◽  
Electronic Hardware

This chapter describes two decades of evolution of electronic hardware for fuzzy computing, and discusses the new trends and challenges that are currently being faced in this field. Firstly the authors analyze the main design approaches performed since first fuzzy chip designs were published and until the consolidation of reconfigurable hardware: the digital approach and the analog approach. Secondly, the evolution of fuzzy hardware based on reconfigurable devices, from traditional field programmable gate arrays to complex system-on-programmable chip solutions, is described and its relationship with the scalability issue is explained. The reconfigurable approach is completed by analyzing a cutting edge design methodology known as dynamic partial reconfiguration and by reviewing some evolvable fuzzy hardware designs. Lastly, regarding fuzzy data-mining processing, the main proposals to speed up data-mining workloads are presented: multiprocessor architectures, reconfigurable hardware, and high performance reconfigurable computing.

Field Programmable Processor Array: Reconfigurable Computing for Space

2007 ◽  
Author(s):  
Gregory W. Donohoe ◽  
David M. Buehler ◽  
K. Joseph Hass ◽  
William Walker ◽  
Pen-Shu Yeh
Keyword(s):  
Reconfigurable Computing ◽  
Processor Array ◽  
Field Programmable

Field programmable spin-logic realized with tunnelling-magnetoresistance devices

2002 ◽  
Vol 46 (5) ◽  
pp. 639-643 ◽  
Author(s):  
R. Richter ◽  
H. Boeve ◽  
L. Bär ◽  
J. Bangert ◽  
G. Rupp ◽  
...  
Keyword(s):  
Spin Logic ◽  
Field Programmable ◽  
Tunnelling Magnetoresistance

Field programmable spin-logic based on magnetic tunnelling elements

2002 ◽  
Vol 240 (1-3) ◽  
pp. 127-129 ◽  
Author(s):  
R. Richter ◽  
H. Boeve ◽  
L. Bär ◽  
J. Bangert ◽  
U.K. Klostermann ◽  
...  
Keyword(s):  
Spin Logic ◽  
Field Programmable

scholarly journals Proposal of the CAD System for Melanoma Detection Using Reconfigurable Computing

Sensors ◽  
2020 ◽  
Vol 20 (11) ◽  
pp. 3168 ◽  
Author(s):  
Wysterlânya K. P. Barros ◽  
Daniel S. Morais ◽  
Felipe F. Lopes ◽  
Matheus F. Torquato ◽  
Raquel de M. Barbosa ◽  
...  
Keyword(s):  
Cancer Detection ◽  
Reconfigurable Computing ◽  
Software Implementation ◽  
Cad System ◽  
Gate Arrays ◽  
Melanoma Detection ◽  
Field Programmable ◽  
Open Access Database ◽  
Programmable Gate Arrays ◽  
Dedicated Hardware

This work proposes dedicated hardware to real-time cancer detection using Field-Programmable Gate Arrays (FPGA). The presented hardware combines a Multilayer Perceptron (MLP) Artificial Neural Networks (ANN) with Digital Image Processing (DIP) techniques. The DIP techniques are used to extract the features from the analyzed skin, and the MLP classifies the lesion into melanoma or non-melanoma. The classification results are validated with an open-access database. Finally, analysis regarding execution time, hardware resources usage, and power consumption are performed. The results obtained through this analysis are then compared to an equivalent software implementation embedded in an ARM A9 microprocessor.

scholarly journals Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-11 ◽  
Author(s):  
JunKyu Lee ◽  
Gregory D. Peterson ◽  
Robert J. Harrison ◽  
Robert J. Hinde
Keyword(s):  
Monte Carlo ◽  
Reconfigurable Computing ◽  
Random Number ◽  
Random Number Generation ◽  
Random Number Generators ◽  
Fine Grained ◽  
Number Generation ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Parallel Random Number Generators

The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such as Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical properties. In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx XC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results. HASPRNG includes the reconfigurable logic for FPGAs along with a programming interface which performs integer random number generation. To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo π-estimator for the Cray XD1. The RC Monte Carlo π-estimator shows a 19.1× speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1. In this paper we describe the FPGA implementation for HASPRNG and a π-estimator example application exploiting the fine-grained parallelism and mathematical properties of the SPRNG algorithm.

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