scholarly journals Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-11 ◽  
Author(s):  
JunKyu Lee ◽  
Gregory D. Peterson ◽  
Robert J. Harrison ◽  
Robert J. Hinde

The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such as Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical properties. In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx XC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results. HASPRNG includes the reconfigurable logic for FPGAs along with a programming interface which performs integer random number generation. To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo π-estimator for the Cray XD1. The RC Monte Carlo π-estimator shows a 19.1× speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1. In this paper we describe the FPGA implementation for HASPRNG and a π-estimator example application exploiting the fine-grained parallelism and mathematical properties of the SPRNG algorithm.

1992 ◽  
Vol 03 (03) ◽  
pp. 561-564 ◽  
Author(s):  
J.R. HERINGA ◽  
H.W.J. BLÖTE ◽  
A. COMPAGNER

The list of primitive binary trinomials with a degree equal to a Mersenne exponent is extended. The newly found primitive trinomials have a degree equal to the 29th and 30th Mersenne exponent. These trinomials enable the construction of new, high-performance random-number generators for use in large-scale Monte Carlo simulations.


2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.


2014 ◽  
Vol 573 ◽  
pp. 181-186 ◽  
Author(s):  
G.P. Ramesh ◽  
A. Rajan

—Field-programmable gate array (FPGA) optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. A random number generator (RNG) is a computational or physical device designed to generate a sequence of numbers or symbols that lack any pattern, i.e. appear random. The many applications of randomness have led to the development of several different methods for generating random data. Several computational methods for random number generation exist, but often fall short of the goal of true randomness though they may meet, with varying success, some of the statistical tests for randomness intended to measure how unpredictable their results are (that is, to what degree their patterns are discernible).LUT-SR Family of Uniform Random Number Generators are able to handle randomness only based on seeds that is loaded in the look up table. To make random generation efficient, we propose new approach based on SRAM storage device.Keywords: RNG, LFSR, SRAM


Author(s):  
E. Jack Chen

A facility for generating sequences of pseudorandom numbers is a fundamental part of computer simulation systems. Furthermore, multiple independent streams of random numbers are often required in simulation studies, for instance, to facilitate synchronization for variance-reduction purposes, and for making independent replications. A portable set of software utilities is described for uniform random-number generation. It provides for multiple generators (streams) running simultaneously, and each generator (stream) has its sequence of numbers partitioned into many long disjoint contiguous substreams. Simple procedure calls allow the user to make any generator “jump” ahead/back v steps (random numbers). Implementation issues are discussed. An efficient and portable code is also provided to implement the package. The basic underlying generator CMRG (combined Multiple Recursive Generator) combines two multiple recursive random number generators with a period length of approximately 2191 (˜ 3.1× 1057), good speed, and excellent theoretical properties.


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