In-situ characterization of Ga2O passivation of In0.53Ga0.47As prior to high-k dielectric atomic layer deposition

Aluminum-based high-k dielectric materials have been studied for their potential use as passivation for SiC devices. Metal-insulator-semiconductor structures were prepared and their dielectric properties were analyzed using capacitance-voltage and current-voltage measurements. Atomic layer deposition was used for the deposition of dielectric layers consisting of AlN with or without a buffer layer of SiO2, and also a stack of alternating AlN and Al2O3 layers. It has been observed that AlN has a polycrystalline structure which provides leakage paths for the current through the grain boundaries. However, adding alternate amorphous layers of Al2O3 prevent this leakage and give better overall dielectric properties. It is also concluded that the breakdown of the dielectric starts from the degradation of the thin interfacial SiO2 layer.

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Atomic Layer Deposition and in-Situ Characterization of Yttrium Oxide and Yttria-Stabilized Zirconia

ECS Meeting Abstracts ◽

10.1149/ma2015-02/26/988 ◽

2015 ◽

Keyword(s):

Atomic Layer Deposition ◽

Yttrium Oxide ◽

Atomic Layer ◽

Yttria Stabilized Zirconia ◽

Stabilized Zirconia ◽

In Situ Characterization ◽

Layer Deposition

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In situ characterization of atomic layer deposition processes by a mass spectrometer

Journal de Physique IV (Proceedings) ◽

10.1051/jp4:19998127 ◽

1999 ◽

Vol 09 (PR8) ◽

pp. Pr8-1021-Pr8-1028 ◽

Cited By ~ 19

Author(s):

M. Ritala ◽

M. Juppo ◽

K. Kukli ◽

A. Rahtu ◽

M. Leskelä

Keyword(s):

Atomic Layer Deposition ◽

Mass Spectrometer ◽

Atomic Layer ◽

In Situ Characterization ◽

Layer Deposition ◽

Deposition Processes

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In situ characterization of atomic layer deposition of SrTiO3

Journal de Physique IV (Proceedings) ◽

10.1051/jp4:20013115 ◽

2001 ◽

Vol 11 (PR3) ◽

pp. Pr3-923-Pr3-930 ◽

Cited By ~ 15

Author(s):

A. Rahtu ◽

T. Hänninen ◽

M. Ritala

Keyword(s):

Atomic Layer Deposition ◽

Atomic Layer ◽

In Situ Characterization ◽

Layer Deposition

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In Situ Studies of III-V Surfaces and High-K Atomic Layer Deposition

Solid State Phenomena ◽

10.4028/www.scientific.net/ssp.195.90 ◽

2012 ◽

Vol 195 ◽

pp. 90-94 ◽

Cited By ~ 1

Author(s):

B. Brennan ◽

S. McDonnell ◽

D. Zhernokletov ◽

H. Dong ◽

C.L. Hinkle ◽

...

Keyword(s):

Atomic Layer Deposition ◽

Integrated Circuit ◽

Surface Passivation ◽

Tunneling Current ◽

Atomic Layer ◽

Formidable Challenge ◽

Layer Deposition ◽

High K ◽

High K Dielectric

Atomic layer deposition (ALD) of high dielectric constant (high-k) materials for ULSI technologies is now widely adopted in Si-based CMOS production. Extending the scaling of integrated circuit technology has now resulted in the investigation of transistors incorporating alternative channel materials, such as III-V compounds. The control of the interfacial chemistry between a high-k dielectric and III-V materials presents a formidable challenge compared to that surmounted by Si-based technologies. The bonding configuration is obviously more complicated for a compound semiconductor, and thus an enhanced propensity to form interfacial defects is anticipated, as well as the need for surface passivation methods to mitigate such defects. In this work, we outline our recent results using in-situ methods to study the ALD high-k/III-V interface. We begin by briefly summarizing our results for III-As compounds, and then further discuss recent work on III-P and III-Sb compounds. While arsenides are under consideration for nMOS devices, antimonides are of interest for pMOS. InP is under consideration for quantum well channel MOS structures in order to serve as a better nMOS channel interface. In all cases, a high-k dielectric interface is employed to limit off-state tunneling current leakage.

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